EPM9320ALC84-15 vs EPM9320ALI84-10N Comparison
Detailed side-by-side comparison of EPM9320ALC84-15 by Altera and EPM9320ALI84-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-15 | EPM9320ALI84-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 CPLD | MAX 9000 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 | 6,000 to 12,000 |
| Propagation Delay (tPD) | 16 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O | 56 | — |
| Logic Array Blocks (LABs) | 16 | 20 |
| Technology | CMOS, EEPROM-based configuration | — |
| Package | 84-pin PLCC (S-PQCC-J84, J-lead) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Mounting Type | Through-hole / socket | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| RoHS Status | [DATA_NEEDED: rohs status] | — |
| Moisture Sensitivity Level (MSL) | MSL-3 (168 hours per fpgalink.com) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead free status] | — |
| RoHS3 Compliance | ROHS3 Compliant (per fpgalink.com listing) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | — | CMOS EEPROM |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Configuration Memory | — | EEPROM, non-volatile |