EPM9320ALI84-10N - 320-Macrocell 10ns MAX 9000 CPLD | Altera
MPN: EPM9320ALI84-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $21.95 | $21,950.00 |
Drop-in alternatives for EPM9320ALI84-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320ALI84-10
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View Datasheet βEPM9320ALC84-10N
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View Datasheet βEPM9320ALC84-15
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View Datasheet βEPM9320ALC84-20
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View Datasheet βEPM9320ALI84-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 20 |
| User I/O Pins | 56 |
| Pin-to-Pin Delay | 10 ns |
| Maximum Counter Frequency | 144.9 MHz |
| VCCINT (Core Supply) | 5.0 V |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Operating Temperature | -40C to +85C (industrial) |
| Configuration Memory | EEPROM, non-volatile |
EPM9320ALI84-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank-dependent function) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | VCCINT β Core supply, 5.0 V |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | VCCIO β I/O supply, 3.3 V or 5.0 V |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | GND β Ground |
| Pin 50 | TDI β JTAG Test Data In |
| Pin 51 | TMS β JTAG Test Mode Select |
| Pin 52 | TCK β JTAG Test Clock |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | VCCINT β Core supply, 5.0 V |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | GND β Ground |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ALI84-10N is suitable for 6 applications: High-Performance Address Decoding, Bus Arbitration and Interface Bridging, Industrial Control and Instrumentation Logic, Telecom and Networking Glue Logic, Legacy TTL/CMOS MSI Replacement, State-Machine and Sequencer Designs.
High-Performance Address Decoding
The EPM9320ALI84-10N is well suited for high-speed memory and peripheral address decoding in 5 V microprocessor systems. Its 10 ns pin-to-pin delay and 144.9 MHz counter frequency allow it to generate chip-select and bank-select signals ahead of any 386/486/Pentium-era CPU access time, eliminating wait states. The 320 macrocells easily absorb full 24- or 32-bit address-decode trees, while the 56 user I/Os provide ample chip-select outputs for large memory maps. Placed between the CPU address bus and the peripheral chip-select pins, the device replaces multiple 74LS/74FTTL decoder packages. The 5.0 V VCCINT with TTL-compatible inputs makes it a drop-in upgrade from legacy discrete decode logic.
Recommended
Bus Arbitration and Interface Bridging
Multi-master bus systems (VME, ISA, PCI in 5 V implementations) require deterministic arbitration logic that a CPLD delivers more cleanly than discrete MSI. The EPM9320ALI84-10N's 10 ns propagation delay ensures grant signals settle within a single bus clock, while its 320 macrocells implement full priority encoders, bus-master handshakes, and wait-state generators. Separate VCCINT (5 V) and VCCIO (3.3 V or 5 V) rails let the same CPLD bridge 5 V legacy peripherals to 3.3 V ASICs on the same PCB. JTAG ISP allows last-minute re-spin of the arbitration algorithm without board rework - critical when debugging contention issues on prototype hardware.
Recommended
Industrial Control and Instrumentation Logic
Factory-automation controllers, PLCs, and instrument front-ends benefit from the EPM9320ALI84-10N's industrial -40C to +85C operating range and 5 V tolerance. The 320 macrocells hold encoder/decoder logic, pulse-train generators, PWM modulators, and fault-handling state machines that previously required multiple PALs. The 84-pin PLCC package and through-hole socket compatibility ease hand-rework on legacy industrial boards where PLD logic must be replaced. The JTAG ISP enables field firmware updates over the JTAG header without removing the board from service - a major reliability advantage in 24/7 industrial environments.
Recommended
Telecom and Networking Glue Logic
Telecom line cards, T1/E1 framers, and legacy router designs use the EPM9320ALI84-10N as glue logic between network processors, PHY chips, and TDM buses. The 10 ns pin-to-pin delay and 144.9 MHz counter frequency handle HDLC framing bit-stuffing and clock-recovery gating that FPGAs would overspec. Multi-voltage I/O (3.3 V/5 V VCCIO) lets the same CPLD interface 5 V line-interface ICs and 3.3 V network processors without external level shifters. The 56 user I/Os accommodate full T1/E1 timeslot-assignment matrices and front-panel LED drivers in a single device.
Recommended
Legacy TTL/CMOS MSI Replacement
Designers maintaining 1980s and 1990s equipment often replace 10-30 discrete 74LS, 74F, 74ALS, and 74HC MSI packages with a single EPM9320ALI84-10N. The 320 macrocells and 56 I/Os are more than enough to absorb a full board of glue logic, while the 10 ns speed grade matches or beats the original discrete logic. The non-volatile EEPROM configuration eliminates the need for separate PAL/GAL programming hardware, and the JTAG ISP supports post-assembly board bring-up. This consolidation reduces power consumption, improves noise margin, and dramatically simplifies board rework.
Recommended
State-Machine and Sequencer Designs
The EPM9320ALI84-10N's MAX architecture is purpose-built for wide state machines: each macrocell contains a flip-flop and a programmable AND/OR array, so 320 macrocells implement state machines with hundreds of states. Application examples include disk-controller sequencers, tape-drive state machines, and printer-engine controllers - all legacy 5 V designs where determinism matters more than LUT density. The 144.9 MHz counter frequency handles fast encoder/decoders (MFM, Manchester, NRZ), while the 10 ns pin-to-pin delay supports 50 MHz state-clock designs. JTAG ISP lets engineers iterate on the state graph without UV-erase cycles.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALI84-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALI84-10 | EPM9320ALC84-10N | EPM9320ALC84-10 | EPM9320ALC84-15 | EPM9320ALC84-20 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Speed Grade (Pin-to-Pin Delay) | -10 (10 ns) | -10 (10 ns) - same | -10 (10 ns) - same | -10 (10 ns) - same | -15 (15 ns) - 50% slower | -20 (20 ns) - 100% slower |
| Operating Temperature | Industrial -40C to +85C | Industrial -40C to +85C - same | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C |
| Lead Finish | Pb-free matte-tin (N suffix) | SnPb (non-N) | Pb-free matte-tin | SnPb (non-N) | Pb-free matte-tin | Pb-free matte-tin |
| Macrocells | 320 | 320 - same | 320 - same | 320 - same | 320 - same | 320 - same |
| User I/O | 56 | 56 - same | 56 - same | 56 - same | 56 - same | 56 - same |
| Maximum Counter Frequency | 144.9 MHz | 144.9 MHz - same | 144.9 MHz - same | 144.9 MHz - same | 118 MHz - 18% slower | 95 MHz - 34% slower |
| VCCINT / VCCIO | 5.0 V / 3.3 V or 5.0 V | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Pb-free matte-tin lead finish for RoHS-compliant designs (vs EPM9320ALI84-10)
- Industrial -40C to +85C operating temperature range (vs EPM9320ALC84-10N)
- Fastest -10 speed grade for time-critical decode paths (vs EPM9320ALC84-15)
Design Notes
VCCINT must always be tied to 5.0 V; VCCIO can be 3.3 V or 5.0 V per bank. According to the Altera MAX 9000 datasheet, place a 0.1 uF decoupling capacitor within 5 mm of every VCCINT pin and every VCCIO pin, plus a 10 uF bulk tantalum near the package. The -10 speed grade has the highest dynamic ICC in the family; for battery-backed or thermally constrained designs, drop to -15 or -20 grade. Estimated: at 50 MHz toggle rate and 30 simultaneously switching outputs at 5 V VCCIO, dynamic current per output is approximately ICC = C * V * f = 10 pF * 5 V * 50 MHz = 2.5 mA per output, so total switching current is around 75 mA, plus quiescent current.
Use a 84-pin PLCC through-hole socket (e.g. 3M 8434-21B1 or equivalent) for easy field replacement on legacy boards. Route JTAG signals (TDI, TDO, TMS, TCK) in a daisy chain with 10 kohm pull-ups on TMS and TCK, per IEEE 1149.1. According to Altera application notes, all unused I/O pins should be configured as outputs driving low to minimize power and avoid floating-input oscillations. Provide a solid ground plane under the PLCC socket to reduce EMI from the high-edge-rate outputs.
Do not mix 3.3 V and 5.0 V devices on the same VCCIO bank - all I/Os in a given bank share one VCCIO rail and must use the same I/O standard. According to the Altera MAX 9000 datasheet, exceeding VCCIO on an input (e.g. driving a 5 V signal into a 3.3 V VCCIO bank) permanently damages the I/O buffer. Use external series resistors or level shifters when interfacing across voltage domains. Also, never leave the JTAG chain disconnected in production - floating TCK or TMS can trigger spurious ISP operations. Tie TMS and TCK through 10 kohm pull-ups to VCCIO.
Compliance Information
RoHS compliant per Altera Pb-free matte-tin (N suffix) lead finish. Not AEC-Q100 qualified - the part targets industrial/consumer, not automotive. Halogen-free status not explicitly stated in the verified web data and marked unknown.
