EPM9320ALC84-20 vs EPM9320LI84-20N Comparison
Detailed side-by-side comparison of EPM9320ALC84-20 by Altera and EPM9320LI84-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-20 | EPM9320LI84-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | β |
| Maximum User I/Os | 212 | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Package | PLCC-84 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Process Technology | 0.5 Β΅m CMOS EEPROM | Advanced CMOS EEPROM |
| Supply Voltage | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | β |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount (PLCC socket compatible) | β |
| Configuration Memory | Non-volatile EEPROM | β |
| Boundary Scan | JTAG IEEE 1149.1 | β |
| Design Software | MAX+PLUS II / Quartus II (legacy) | β |
| RoHS Status | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | β | 6,000 to 12,000 |
| User I/O Pins | β | 60 |
| Total Pins | β | 84 |
| Propagation Delay (tPD) | β | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | β | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | β | 118 MHz |
| Logic Family | β | CMOS, EEPROM-based |
| Programming Interface | β | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |