EPM9320ALC84-20 vs EPM9320LI84-20N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320ALC84-20 disebabkan oleh Altera dan EPM9320LI84-20N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9320ALC84-20 | EPM9320LI84-20N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Kemasan | PLCC-84 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Process Technology | 0.5 µm CMOS EEPROM | Advanced CMOS EEPROM |
| Tegangan Pemberi Arus | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Suhu Operasi | [DATA_NEEDED: commercial or industrial grade] | 0 C to +70 C (commercial) |
| Jenis Pemasangan | Surface Mount (PLCC socket compatible) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| Status RoHS | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Usable Gates | — | 6,000 to 12,000 |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Propagation Delay (tPD) | — | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Logic Family | — | CMOS, EEPROM-based |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |