EPM9320ALI84-10N vs EPM9320BC356-15 Comparison

Detailed side-by-side comparison of EPM9320ALI84-10N by Altera and EPM9320BC356-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320ALI84-10N EPM9320BC356-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture MAX (Multiple Array MatriX), 3rd generation Multiple Array MatriX (MAX) - third generation
Process Technology CMOS EEPROM CMOS EEPROM
Usable Gates 6,000 to 12,000 —
Macrocells 320 320
Logic Array Blocks (LABs) 20 —
User I/O Pins 56 —
Pin-to-Pin Delay 10 ns —
Maximum Counter Frequency 144.9 MHz —
VCCINT (Core Supply) 5.0 V —
VCCIO (I/O Supply) 3.3 V or 5.0 V —
Input Logic Levels TTL-compatible (at 5.0 V VCCINT) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (5.0-V ISP via JTAG)
Package 84-pin PLCC (J-lead, 1.270 mm pitch) 356-ball LBGA (BGA-356, 35x35 mm)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Operating Temperature -40C to +85C (industrial) —
Configuration Memory EEPROM, non-volatile —
Pin-to-Pin Delay (max) — 15 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V typical)
JTAG Interface — IEEE Std. 1149.1 compliant
Programmable Type — In System Programmable
Operating Temperature Grade — Commercial
RoHS Status — [DATA_NEEDED: RoHS compliance status]
Lead-Free — [DATA_NEEDED: lead-free status]

Datasheets & Resources

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