EPM9320ALI84-10N vs EPM9320BC356-15 比較
詳細な並列比較: EPM9320ALI84-10N メーカー: Altera および EPM9320BC356-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320ALI84-10N | EPM9320BC356-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.95 | $31.20 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (5.0-V ISP via JTAG) |
| パッケージ | 84-pin PLCC (J-lead, 1.270 mm pitch) | 356-ball LBGA (BGA-356, 35x35 mm) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount |
| 動作温度 | -40C to +85C (industrial) | — |
| Configuration Memory | EEPROM, non-volatile | — |
| Pin-to-Pin Delay (max) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V typical) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Programmable Type | — | In System Programmable |
| Operating Temperature Grade | — | Commercial |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |