EPM9320ARC208-10 vs EPM9320RC208-15 Comparison

Detailed side-by-side comparison of EPM9320ARC208-10 by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320ARC208-10

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ Last Time Buy
Altera
EPM9320RC208-15

EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera

EPM9320RC208-15 Obsolete

Specification Comparison

Parameter EPM9320ARC208-10 EPM9320RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.40 $0.00
Device Family MAX 9000 MAX 9000
Product Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 320 β€”
Usable Gates 6,000 6,000
Pin-to-Pin Delay (tPD) 10 ns β€”
Maximum Frequency 144.9 MHz β€”
Supply Voltage 5.0 V 5.0 V
Logic Blocks (LABs) 16 β€”
Programmability EEPROM, in-system programmable via JTAG β€”
JTAG Support IEEE Std. 1149.1 compliant β€”
Speed/Power Optimization Per-macrocell programmable, 50% power mode available β€”
Package RQFP-208 (Power Quad Flat Pack) 208-pin RQFP (Power QFP)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Macro Cells β€” 320
Pin-to-Pin Propagation Delay β€” 15 ns (speed grade -15)
Maximum Clock Frequency β€” 117.6 MHz
Configuration Technology β€” EEPROM-based (non-volatile)
In-System Programmability β€” Yes (ISP via JTAG)
JTAG Interface β€” IEEE Std. 1149.1
Package Type β€” 208-BFQFP Exposed Pad
Number of I/O Pins β€” [DATA_NEEDED: user I/O count]
Logic Array Blocks β€” [DATA_NEEDED: LAB count]
Lifecycle Status β€” Obsolete (PDN0706, 2007)

Datasheets & Resources

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