EPM9320ARC208-10 vs EPM9320RC208-15 对比

详细并排对比 EPM9320ARC208-10 出自 Altera 和 EPM9320RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ 最后一次采购

规格对比

参数 EPM9320ARC208-10 EPM9320RC208-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $21.40 $0.00
Device Family MAX 9000 MAX 9000
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Usable Gates 6,000 6,000
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency 144.9 MHz —
电源电压 5.0 V 5.0 V
Logic Blocks (LABs) 16 —
Programmability EEPROM, in-system programmable via JTAG —
JTAG Support IEEE Std. 1149.1 compliant —
Speed/Power Optimization Per-macrocell programmable, 50% power mode available —
封装 RQFP-208 (Power Quad Flat Pack) 208-pin RQFP (Power QFP)
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
最大时钟频率 — 117.6 MHz
Configuration Technology — EEPROM-based (non-volatile)
In-System Programmability — Yes (ISP via JTAG)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
生命周期状态 — Obsolete (PDN0706, 2007)

数据手册与资源

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