EPM9320BC356-15 vs EPM9320GC280-15 Comparison

Detailed side-by-side comparison of EPM9320BC356-15 by Altera and EPM9320GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320BC356-15 EPM9320GC280-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 9000 MAX 9000 (EPM9320)
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Architecture Multiple Array MatriX (MAX) - third generation CMOS EEPROM-based, Multiple Array MatriX (MAX)
Macrocells 320 320
Pin-to-Pin Delay (max) 15 ns —
Process Technology CMOS EEPROM —
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V typical) 4.75 V to 5.25 V
In-System Programmability Yes (5.0-V ISP via JTAG) —
JTAG Interface IEEE Std. 1149.1 compliant —
Package 356-ball LBGA (BGA-356, 35x35 mm) 280-pin Ceramic Pin Grid Array (CPGA-280)
Mounting Type Surface Mount Through-hole (PGA socket)
Programmable Type In System Programmable —
Operating Temperature Grade Commercial —
RoHS Status [DATA_NEEDED: RoHS compliance status] ROHS3 compliant (per fpgalink listing)
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 6,000
Logic Array Blocks (LABs) — 20 (16 macrocells per LAB)
Pin-to-Pin Propagation Delay — 15 ns
Maximum Internal Frequency — 117.6 MHz
Maximum User I/O Pins — 164
I/O Voltage Levels — 3.3 V or 5 V (configurable)
Programmability — 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG
Operating Temperature — 0 C to +70 C (commercial)
MSL Level — 3 (168 hours)
Technology Node — CMOS EEPROM, third-generation MAX

Datasheets & Resources

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