EPM9320BC356-15 vs EPM9320GC280-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320BC356-15 sa pamamagitan ng Altera at EPM9320GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320BC356-15 EPM9320GC280-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 MAX 9000 (EPM9320)
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Architecture Multiple Array MatriX (MAX) - third generation CMOS EEPROM-based, Multiple Array MatriX (MAX)
Macrocells 320 320
Pin-to-Pin Delay (max) 15 ns —
Process Technology CMOS EEPROM —
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V typical) 4.75 V to 5.25 V
In-System Programmability Yes (5.0-V ISP via JTAG) —
JTAG Interface IEEE Std. 1149.1 compliant —
Packhaging 356-ball LBGA (BGA-356, 35x35 mm) 280-pin Ceramic Pin Grid Array (CPGA-280)
Uri ng Pagpapasok Surface Mount Through-hole (PGA socket)
Programmable Type In System Programmable —
Operating Temperature Grade Commercial —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] ROHS3 compliant (per fpgalink listing)
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 6,000
Logic Array Blocks (LABs) — 20 (16 macrocells per LAB)
Pin-to-Pin Propagation Delay — 15 ns
Maximum Internal Frequency — 117.6 MHz
Maximum User I/O Pins — 164
I/O Voltage Levels — 3.3 V or 5 V (configurable)
Programmability — 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG
Temperature na Operasyon — 0 C to +70 C (commercial)
Level ng MSL — 3 (168 hours)
Technology Node — CMOS EEPROM, third-generation MAX

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