EPM9320GC280-15 vs EPM9560GC280-20 Comparison

Detailed side-by-side comparison of EPM9320GC280-15 by Altera and EPM9560GC280-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320GC280-15 EPM9560GC280-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $92.50 $360.00
Family MAX 9000 (EPM9320) MAX 9000
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Architecture CMOS EEPROM-based, Multiple Array MatriX (MAX) β€”
Usable Gates 6,000 12,000
Macrocells 320 560
Logic Array Blocks (LABs) 20 (16 macrocells per LAB) β€”
Pin-to-Pin Propagation Delay 15 ns β€”
Maximum Internal Frequency 117.6 MHz β€”
Maximum User I/O Pins 164 β€”
Supply Voltage (VCC) 4.75 V to 5.25 V β€”
I/O Voltage Levels 3.3 V or 5 V (configurable) β€”
Programmability 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG β€”
Package 280-pin Ceramic Pin Grid Array (CPGA-280) 280-pin CPGA (Ceramic Pin Grid Array)
Mounting Type Through-hole (PGA socket) Through-Hole (CPGA socket)
Operating Temperature 0 C to +70 C (commercial) [DATA_NEEDED: commercial/industrial/military grade]
MSL Level 3 (168 hours) β€”
RoHS Status ROHS3 compliant (per fpgalink listing) [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant]
Technology Node CMOS EEPROM, third-generation MAX β€”
Maximum User I/O β€” 212
Pin-to-Pin Delay β€” 20 ns (speed grade -20)
Counter Frequency (max) β€” 100 MHz
Supply Voltage (VCCINT) β€” 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage β€” 3.3 V or 5.0 V configurable
Process Technology β€” CMOS EEPROM
In-System Programming β€” Yes, via IEEE 1149.1 JTAG

Datasheets & Resources

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