EPM9320GC280-15 vs EPM9560GC280-20 तुलना
विस्तृत दोनों ओर की तुलना EPM9320GC280-15 द्वारा Altera और EPM9560GC280-20 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 Obsoleteविशेषता तुलना
| पैरामीटर | EPM9320GC280-15 | EPM9560GC280-20 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 9000 (EPM9320) | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, Multiple Array MatriX (MAX) | — |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 320 | 560 |
| Logic Array Blocks (LABs) | 20 (16 macrocells per LAB) | — |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Maximum User I/O Pins | 164 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| I/O Voltage Levels | 3.3 V or 5 V (configurable) | — |
| Programmability | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG | — |
| पैकेज | 280-pin Ceramic Pin Grid Array (CPGA-280) | 280-pin CPGA (Ceramic Pin Grid Array) |
| माउंटिंग प्रकार | Through-hole (PGA socket) | Through-Hole (CPGA socket) |
| ऑपरेटिंग तापमान | 0 C to +70 C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| MSL स्तर | 3 (168 hours) | — |
| RoHS स्थिति | ROHS3 compliant (per fpgalink listing) | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] |
| Technology Node | CMOS EEPROM, third-generation MAX | — |
| Maximum User I/O | — | 212 |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Counter Frequency (max) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage | — | 3.3 V or 5.0 V configurable |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG |