EPM9320GC280-20 vs EPM9560GC280-15N Comparison

Detailed side-by-side comparison of EPM9320GC280-20 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320GC280-20 EPM9560GC280-15N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Usable Gates 6000 (approx.) 12,000 (typical)
Logic Array Blocks (LABs) 20 (16 macrocells each, typical for MAX 9000) —
Maximum Operating Frequency 100 MHz (internal counter) —
Propagation Delay (tpd) 23 ns (approx., -20 speed grade) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS EEPROM —
In-System Programmability Yes (5.0-V ISP via JTAG) Yes (5.0-V ISP via JTAG)
JTAG Support IEEE Std. 1149.1 compliant —
Package 280-pin Ceramic Pin Grid Array (CPGA) CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Operating Temperature [DATA_NEEDED: operating temperature grade] —
Mounting Type Through-Hole (PGA socket) —
RoHS Status unknown —
Configuration Memory EEPROM (non-volatile, instant-on) —
Device Family — MAX 9000
Product Type — EE PLD / CPLD
Macrocell Count — 560
Propagation Delay (tPD) — 16.6 ns
Maximum Clock Frequency — 117.6 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Maximum Supply Voltage — 5.25 V
Logic Technology — CMOS EEPROM
Boundary-Scan (JTAG) — IEEE Std. 1149.1 compliant
Package Code — PGA / CPGA280
Terminal Form — PIN/PEG
Operating Temperature Grade — Commercial
Architecture — Multiple Array MatriX (MAX) 3rd generation

Datasheets & Resources

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