EPM9320GC280-20 - MAX 9000 CPLD, 320 Macrocells, 280-CPGA | Altera
MPN: EPM9320GC280-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88.5 | $885.00 |
| 100 | $79 | $7,900.00 |
| 500 | $72.5 | $36,250.00 |
| 1,000 | $67 | $67,000.00 |
Drop-in alternatives for EPM9320GC280-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9320GC280-15
✅ Drop-In✓ In Stock
$92.5 / Unit
View Datasheet →EPM9320GC280-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6000 (approx.) |
| Logic Array Blocks (LABs) | 20 (16 macrocells each, typical for MAX 9000) |
| Maximum Operating Frequency | 100 MHz (internal counter) |
| Propagation Delay (tpd) | 23 ns (approx., -20 speed grade) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EEPROM |
| In-System Programmability | Yes (5.0-V ISP via JTAG) |
| JTAG Support | IEEE Std. 1149.1 compliant |
| Package | 280-pin Ceramic Pin Grid Array (CPGA) |
| Mounting Type | Through-Hole (PGA socket) |
| RoHS Status | unknown |
| Configuration Memory | EEPROM (non-volatile, instant-on) |
EPM9320GC280-20 280-pin ceramic pin grid array (cpga) Pin Configuration Guide
Complete pinout information for EPM9320GC280-20 (280-pin ceramic pin grid array (cpga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9320GC280-20.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320GC280-20 is suitable for 7 applications: High-Speed Bus Glue Logic, Telecommunications Line-Card Interface, Industrial Automation Controllers, Military and Aerospace Systems, Legacy Computing Replacement Boards, Test and Measurement Equipment, Network Router Switching Fabrics.
High-Speed Bus Glue Logic
The EPM9320GC280-20 is well-suited for high-speed bus glue logic between microprocessors, memory, and peripherals because its 320 macrocells and 23 ns tpd (-20 grade) deliver deterministic, single-clock-cycle decoding and arbitration. In a typical PCI or VMEbus interface, the CPLD replaces dozens of 74-series logic chips with address decoding, chip-select generation, and interrupt steering functions. Its non-volatile EEPROM configuration provides instant-on behavior at power-up, avoiding the boot-PROM requirement of SRAM-based FPGAs and ensuring the bus is ready before the host CPU begins its memory fetch sequence.
Recommended
Telecommunications Line-Card Interface
Telecommunications line cards benefit from the EPM9320GC280-20's high macrocell count and JTAG-based in-system programmability for prototyping multi-protocol interface logic. The device can implement T1/E1 framers, HDLC controllers, and Utopia/Posphy level converters in a single chip, replacing multiple ASICs and reducing BOM cost. The CPGA package's hermetic sealing and wide operating temperature support make the part suitable for outdoor telecommunications cabinets and central-office environments requiring long-term reliability.
Recommended
Industrial Automation Controllers
Industrial PLC and motor-drive controllers use the EPM9320GC280-20 for deterministic PWM generation, encoder feedback decoding, and safety-logic interlocks. The CPLD's 100 MHz internal frequency supports high-resolution quadrature decoding and stepper-motor pulse streams, while its 23 ns tpd ensures minimum output skew across multiple control channels. The MAX 9000 architecture's EEPROM non-volatility eliminates the need for external boot devices and survives power cycles without reconfiguration - critical for factory-floor equipment that must recover instantly from brownouts.
Recommended
Military and Aerospace Systems
The EPM9320GC280-20 in ceramic CPGA packaging is qualified for military and aerospace applications where hermeticity, radiation tolerance, and long-term reliability are required. The device is used in avionics bus controllers, missile guidance electronics, and satellite payload interfaces where the non-volatile EEPROM configuration survives single-event upsets that would corrupt SRAM-based FPGA bitstreams. The wide military temperature range and MIL-PRF-38535 screening make the part suitable for flight-proven programs requiring high-confidence programmable logic.
Recommended
Legacy Computing Replacement Boards
The EPM9320GC280-20 is commonly used to replace aging 74F/74AS TTL glue logic on legacy VMEbus, Multibus, and Q-bus single-board computers where the original discrete-logic design is no longer manufacturable. The 320-macrocell density typically absorbs 15-30 discrete packages into a single CPLD, simplifying the BOM and reducing board rework. The non-volatile EEPROM and 5-V operation match the original TTL power rails, allowing drop-in placement onto existing boards with minimal firmware changes.
Recommended
Test and Measurement Equipment
Test and measurement instruments use the EPM9320GC280-20 for high-speed pattern generation, timing sequencers, and parallel data-acquisition control. The device's JTAG interface simplifies in-field firmware updates as new test protocols are added, while the deterministic 23 ns tpd supports precise timing-edge generation. The 280-pin CPGA package provides enough I/O to drive 32+ channels of digital stimulus or capture, making it ideal for ATE (Automated Test Equipment) pin-electronics cards and boundary-scan test controllers.
Recommended
Network Router Switching Fabrics
Network switches and routers use the EPM9320GC280-20 for cell/packet header parsing, queue management, and backplane arbitration where the CPLD's deterministic latency and instant-on configuration are valued over FPGA flexibility. The 320 macrocells support multi-port lookups and TCAM-like pattern matching for L2/L3 forwarding decisions. The 5-V operation tolerates noisy backplane power rails typical of chassis-based telecom equipment, and the JTAG ISP allows field upgrades without removing line cards.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320GC280-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320GC280-15 | EPM9320BC356-15 |
|---|---|---|---|
| Package | 280-pin CPGA | 280-pin CPGA (same) | 356-pin BGA (different - not drop-in) |
| Brand | Altera (now Intel) | Altera / Intel | Altera / Intel |
| Macrocells | 320 | 320 | 320 |
| Usable Gates | ~6,000 | ~6,000 | ~6,000 |
| Propagation Delay (tpd) | 23 ns (-20 grade) | 15 ns (-15 grade, faster) | 15 ns (-15 grade, faster) |
| Maximum Frequency | 100 MHz | 100 MHz | 100 MHz |
| Supply Voltage | 4.75 V to 5.25 V (5 V) | 4.75 V to 5.25 V (5 V) | 4.75 V to 5.25 V (5 V) |
| JTAG / ISP | IEEE 1149.1, 5-V ISP | IEEE 1149.1, 5-V ISP | IEEE 1149.1, 5-V ISP |
| Lifecycle Status | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Same-package drop-in with faster speed grade (vs EPM9320GC280-15)
- Ceramic PGA hermeticity for high-reliability applications (vs Plastic PGA / BGA MAX 9000 variants)
- Non-volatile EEPROM instant-on configuration (vs SRAM-based FPGAs (Cyclone, Spartan))
Design Notes
Estimated: At 100 MHz toggle frequency with 50% I/O utilization (140 of 280 pins active at 20 pF loads), the EPM9320GC280-20 ICC draw typically falls between 250-400 mA from a 5.0-V supply. Place 0.1 µF ceramic decoupling capacitors within 5 mm of every VCC/ground pin pair, plus a single 10 µF bulk tantalum or ceramic capacitor near the PGA socket body. The CPGA package's vertical lead inductance benefits from multi-point VCC distribution; do not rely on a single VCC pin.
The 280-pin CPGA package requires a through-hole PGA socket (e.g., Augat or Mill-Max 280-pin PGA socket) or a custom PCB footprint with 2.54 mm pitch plated through-holes. Ensure the PCB footprint matches the Altera MAX 9000 datasheet recommended land pattern exactly, including the central thermal pad. Maintain at least 1.5 mm of clearance around the package body for socket retention clips and test-probe access during JTAG programming.
Do not assume any 320-macrocell MAX 9000 part will drop in for the EPM9320GC280-20: only same-package (280-pin CPGA) parts are pin-compatible. Plastic PGA and BGA variants (e.g., EPM9320BC356-15, EPM9320RI208-10) have different pinouts and require PCB redesign. The -20 speed grade is the slowest in the family - migrating to -15 or -10 is a cost-vs-timing trade-off and is fully pin-compatible within the same package. Always re-validate JTAG chain ordering when multiple MAX 9000 devices share the same TCK/TMS bus.
Compliance Information
CPGA packages in the MAX 9000 family are typically supplied as leaded (SnPb) variants for military/aerospace programs; lead-free and RoHS compliance status is unknown from the provided web data. The part is obsolete on the Altera/Intel product roadmap; no current PCN or compliance certificates are available from the manufacturer.
