EPM9320RC208-15N vs EPM9320RI208-10N 比較
詳細並排比較 EPM9320RC208-15N 由 Intel 與 EPM9320RI208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RC208-15N | EPM9320RI208-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | Complex Programmable Logic Device (CPLD) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Flip-Flops | 484 | — |
| Configurable I/O Lines | 128 | — |
| Propagation Delay (tPD) | 15 ns | — |
| 最大時脈頻率 | 117.6 MHz | — |
| 供應電壓 | 5.0 V | 5 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Technology | CMOS EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (JTAG/ISP) |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Terminal Pitch | 0.5 mm | — |
| 工作溫度範圍 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| 安裝類型 | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Configuration Memory | — | EEPROM (non-volatile) |
| Lead Finish | — | Lead-free (matte tin) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |