EPM9320RC208-20 vs EPM9320RC208-15 Comparison
Detailed side-by-side comparison of EPM9320RC208-20 by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-20 | EPM9320RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.90 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 320 | β |
| Logic Array Blocks (LABs) | 20 | β |
| Usable Gates | 6,000 | 6,000 |
| Maximum I/O Pins | 132 | β |
| Propagation Delay (tPD max) | 20 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Programming Technology | EEPROM, in-system programmable (ISP) | β |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | [DATA_NEEDED: operating temperature range] |
| Package | 208-RQFP, exposed pad (208-BFQFP) | 208-pin RQFP (Power QFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | β |
| Process Technology | CMOS, 5.0 V EEPROM | β |
| Reprogrammability | Yes, unlimited ISP cycles | β |
| Device Family | β | MAX 9000 |
| Macro Cells | β | 320 |
| Pin-to-Pin Propagation Delay | β | 15 ns (speed grade -15) |
| Maximum Clock Frequency | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM-based (non-volatile) |
| In-System Programmability | β | Yes (ISP via JTAG) |
| JTAG Interface | β | IEEE Std. 1149.1 |
| Package Type | β | 208-BFQFP Exposed Pad |
| Number of I/O Pins | β | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | β | [DATA_NEEDED: LAB count] |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | β | Obsolete (PDN0706, 2007) |