EPM9320RC208-20 vs EPM9320RC208-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-20 sa pamamagitan ng Altera at EPM9320RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320RC208-20 EPM9320RC208-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Logic Array Blocks (LABs) 20 —
Usable Gates 6,000 6,000
Maximum I/O Pins 132 —
Propagation Delay (tPD max) 20 ns —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
Programming Technology EEPROM, in-system programmable (ISP) —
Boundary-Scan Interface IEEE Std. 1149.1 (JTAG) —
Temperature na Operasyon 0 °C to 70 °C (commercial) [DATA_NEEDED: operating temperature range]
Packhaging 208-RQFP, exposed pad (208-BFQFP) 208-pin RQFP (Power QFP)
Uri ng Pagpapasok Surface Mount Surface Mount
Architecture Multiple Array Matrix (MAX), 3rd generation —
Process Technology CMOS, 5.0 V EEPROM —
Reprogrammability Yes, unlimited ISP cycles —
Device Family — MAX 9000
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
Maksimum na Taktiko ng Oras — 117.6 MHz
Volte ng Pagbibigay — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
In-System Programmability — Yes (ISP via JTAG)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
Tindminan RoHS — [DATA_NEEDED: RoHS status]
Katayuan ng Lifecycle — Obsolete (PDN0706, 2007)

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