EPM9320RC208-20N vs EPM9320RC208-15 比較
詳細並排比較 EPM9320RC208-20N 由 Altera 與 EPM9320RC208-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RC208-20N | EPM9320RC208-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | [DATA_NEEDED: LAB count] |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| User I/O Pins | 168 | — |
| 封裝 | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power QFP) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| 最大時脈頻率 | — | 117.6 MHz |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| 生命週期狀態 | — | Obsolete (PDN0706, 2007) |