EPM9320RC208-20N vs EPM9320RC208-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320RC208-20N disebabkan oleh Altera dan EPM9320RC208-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9320RC208-20N | EPM9320RC208-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | [DATA_NEEDED: LAB count] |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Tegangan Pemberi Arus | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| User I/O Pins | 168 | — |
| Kemasan | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power QFP) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Aras MSL | [DATA_NEEDED: MSL level] | — |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Frekuensi Klock Maksimum | — | 117.6 MHz |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Status Lingkungan Hidup | — | Obsolete (PDN0706, 2007) |