EPM9320RC208-20N vs EPM9320RI208-20C Comparison

Detailed side-by-side comparison of EPM9320RC208-20N by Altera and EPM9320RI208-20C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RC208-20N EPM9320RI208-20C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 9000 —
Logic Type Complex Programmable Logic Device (CPLD) —
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks 20 —
Maximum Pin-to-Pin Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage 5.0 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (5.0 V ISP via JTAG)
User I/O Pins 168 —
Package 208-pin RQFP (PowerQuad II) 208-pin RQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] —
RoHS Status [DATA_NEEDED: RoHS status] —
Lead Finish [DATA_NEEDED: lead finish] —
MSL Level [DATA_NEEDED: MSL level] —
Family — MAX 9000
Device Type — EE PLD / CPLD
Logic Elements / Macrocells — 320
Number of Flip-Flops — 484
Logic Array Blocks (LABs) — 16
Maximum Internal Clock Frequency — 100 MHz
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5.0 V
Programmable Interface — JTAG (IEEE Std. 1149.1) BST
Technology — CMOS EEPROM
Operating Temperature (Industrial) — -40C to +85C
Lead-Free / RoHS — Information not confirmed from verified data [DATA_NEEDED: RoHS status]

Datasheets & Resources

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