EPM9320RC208-20N vs EPM9320RI208-20C 比較
詳細並排比較 EPM9320RC208-20N 由 Altera 與 EPM9320RI208-20C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
EPM9320RI208-20C Obsolete規格比較
| 參數 | EPM9320RC208-20N | EPM9320RI208-20C |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks | 20 | — |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| 供應電壓 | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (5.0 V ISP via JTAG) |
| User I/O Pins | 168 | — |
| 封裝 | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD / CPLD |
| Logic Elements / Macrocells | — | 320 |
| Number of Flip-Flops | — | 484 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Clock Frequency | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5.0 V |
| Programmable Interface | — | JTAG (IEEE Std. 1149.1) BST |
| Technology | — | CMOS EEPROM |
| Operating Temperature (Industrial) | — | -40C to +85C |
| Lead-Free / RoHS | — | Information not confirmed from verified data [DATA_NEEDED: RoHS status] |