EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
MPN: EPM9320RI208-20C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 250 | $25.4 | $6,350.00 |
| 500 | $22.1 | $11,050.00 |
Drop-in alternatives for EPM9320RI208-20C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320RC208-20N
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View Datasheet βEPM9320RC208-20
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$21.9 / Unit
View Datasheet βEPM9320RI208-10N
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$27.2 / Unit
View Datasheet βEPM9320RC208-15N
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View Datasheet βEPM9320RC208-15
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View Datasheet βEPM9320RI208-20C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EE PLD / CPLD |
| Logic Elements / Macrocells | 320 |
| Usable Gates | 6,000 |
| Number of Flip-Flops | 484 |
| Logic Array Blocks (LABs) | 16 |
| Maximum Internal Clock Frequency | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5.0 V |
| Programmable Interface | JTAG (IEEE Std. 1149.1) BST |
| In-System Programmability | Yes (5.0 V ISP via JTAG) |
| Technology | CMOS EEPROM |
| Package | 208-pin RQFP (Plastic Quad Flat Pack) |
| Operating Temperature (Industrial) | -40C to +85C |
| Mounting Type | Surface Mount |
EPM9320RI208-20C Pin Configuration
| Pin 1 | I/O β User I/O pin (per MAX 9000 pinout table) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | TDI β JTAG Test Data In (dedicated) |
| Pin 10 | TMS β JTAG Test Mode Select (dedicated) |
| Pin 11 | TCK β JTAG Test Clock (dedicated) |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320RI208-20C is suitable for 6 applications: Bus Bridge and Protocol Translation, Industrial Control Glue Logic, Peripheral I/O Expansion for Microcontrollers, JTAG-Driven Manufacturing Test Fixtures, Legacy 5V System Glue Logic, State-Machine Control in Telecom Backplanes.
Bus Bridge and Protocol Translation
Why EPM9320RI208-20C fits: the 320 macrocells and 484 flip-flops provide ample capacity to bridge 8/16/32-bit buses and to translate between legacy 5V TTL and 3.3 V LVTTL protocols on telecom backplanes. How it is used: typically placed between a microprocessor bus and a peripheral bus, with each macrocell implementing one bit of decode or direction control. The deterministic 20 ns tPD keeps bus-to-bus latency bounded; the 208-pin RQFP supplies the I/O count for wide parallel interfaces. A 5V to 3.3V level-shifting cap is unnecessary because the I/Os are already 3.3 V/5 V tolerant.
Recommended
Industrial Control Glue Logic
Why EPM9320RI208-20C fits: industrial temperature grade (-40C to +85C), deterministic 20 ns propagation delay, and EEPROM non-volatile boot make it ideal for factory-floor glue logic. How it is used: the CPLD decodes address lines, multiplexes discrete I/O, and drives relay/MOSFET predrivers in PLCs and motor-control boards. Instant-on behavior removes boot latency, critical for safety interlocks. The JTAG ISP allows in-field firmware updates on assembled boards, reducing service calls.
Recommended
Peripheral I/O Expansion for Microcontrollers
Why EPM9320RI208-20C fits: 320 macrocells and 208 user I/O pins let the CPLD add many peripheral channels beyond what the host MCU offers natively, without loading the MCU firmware. How it is used: the CPLD sits on the MCU's external bus, with each macrocell implementing one register, PWM, UART, or GPIO. The deterministic 20 ns tPD allows the MCU to read/write the expansion registers in a single cycle, effectively extending the MCU's I/O count by 100+ channels.
Recommended
JTAG-Driven Manufacturing Test Fixtures
Why EPM9320RI208-20C fits: the built-in IEEE 1149.1 JTAG boundary-scan interface and 5V ISP allow fixture designers to reuse the same device both as a control element and as a boundary-scan chain node. How it is used: in bed-of-nails test fixtures and ATE interfaces, the CPLD generates test vectors, captures responses, and routes them to the JTAG controller. 484 flip-flops provide plenty of registered capture points, and the JTAG TAP is accessible in-system for fixture self-test.
Recommended
Legacy 5V System Glue Logic
Why EPM9320RI208-20C fits: a single 5.0 V supply, 3.3 V or 5 V tolerant I/O, and a non-volatile EEPROM boot image keep it compatible with vintage 5V microprocessor designs where 3.3 V-only CPLDs cannot operate. How it is used: replaces discrete 74LS/74F glue-logic in VME bus, Multibus, and STD-32 systems. 320 macrocells easily absorb what used to be a board full of small-scale integration; the 208-pin RQFP keeps the board area similar. JTAG ISP allows firmware updates on legacy systems that cannot be reflashed.
Recommended
State-Machine Control in Telecom Backplanes
Why EPM9320RI208-20C fits: deterministic 20 ns pin-to-pin delay makes it ideal for state machines that must respond to asynchronous events within a fixed window, such as T1/E1 framer control, line-card reset sequencers, and clock-distribution state machines. How it is used: each macrocell hosts a portion of a Moore/Mealy machine with D/T/JK/SR flip-flop modes, all clocked from a single global clock at up to 100 MHz. The 5V-tolerant I/O interfaces cleanly to ECL/TTL line-driver ICs of the same era.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320RI208-20C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320RC208-20N | EPM9320RC208-20 | EPM9320RI208-10N | EPM9320RC208-15N | EPM9320RC208-15 |
|---|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Pin-to-Pin tPD | 20 ns | 20 ns | 20 ns | 10 ns | 15 ns | 15 ns |
| Max Clock Frequency | 100 MHz | 100 MHz | 100 MHz | 125 MHz | 111 MHz | 111 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade with deterministic 20 ns tPD (vs EPM9320RC208-20N)
- In-system programmability via JTAG (vs EPM9320GC280-15 (non-ISP variant))
- 320 macrocells in 208-pin RQFP (vs EPM9320LC84-15 (smaller package))
Design Notes
The EPM9320RI208-20C requires a single 5.0 V VCC supply that must rise monotonically at power-up to avoid EEPROM programming lockouts. Provide one 0.1 uF ceramic decoupling capacitor on every VCC pin pair and at least one 10 uF bulk tantalum or ceramic capacitor near the package. The MAX 9000 datasheet specifies that during input transitions, signals may undershoot to -2.0 V or overshoot to 7.0 V for periods under 20 ns under no-load conditions - clamp with series resistors if long cables are involved.
Place JTAG header (TCK, TMS, TDI, TDO) within 5 cm of the device with no stubs on the TCK line. Use 10 kohm pull-ups on TMS and TDI, and a 10 kohm pull-down on TCK as recommended by the MAX 9000 family datasheet. The 208-pin RQFP (0.5 mm pitch) requires fine-pitch PCB layout - use 4-layer stackup with continuous ground plane under the device to minimize ground bounce on simultaneous switching outputs.
Do not apply 5 V signals to the device before VCC reaches its minimum operating threshold - the EEPROM ISP charge pump requires VCC to be valid. Do not exceed 20 ns input undershoot/overshoot durations longer than 20 ns without external clamping. When migrating designs from EPM9320ARC208-10 (10 ns tPD) to the slower RI208-20C variant, re-time any path that previously met its budget at the edge of the 10 ns spec.
Compliance Information
RoHS, REACH, and lead-free status were not confirmed from the verified web data; the MAX 9000 family predates widespread RoHS adoption. AEC-Q100 not applicable (CPLD, not an automotive-qualified IC by default).
