EPM9320RI208-10N vs EPM9320ARI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RI208-10N sa pamamagitan ng Altera at EPM9320ARI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM9320RI208-10N | EPM9320ARI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 20 |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| Volte ng Pagbibigay | 5 V | 4.5 V to 5.5 V |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | — |
| Packhaging | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (S-PQFP-G208) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG/ISP) | — |
| Hanay ng Temperature na Operasyon | -40C to +85C (industrial) | — |
| Tindminan RoHS | Compliant (N suffix = lead-free) | unknown |
| Lead Finish | Lead-free (matte tin) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Maximum Operating Frequency | — | 144.9 MHz |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Temperature na Operasyon | — | -40 C to +85 C (industrial) |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system (ISP) via IEEE 1149.1 JTAG |
| Global Dedicated Inputs | — | 16 |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |