EPM9320RI208-20 vs EPM9320RC208-15 Comparison

Detailed side-by-side comparison of EPM9320RI208-20 by Intel and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RI208-20 EPM9320RC208-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Usable Gates 6,000 6,000
Propagation Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (VCC) 5.0 V —
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) —
Programmable Interconnect Programmable Interconnect Array (PIA) —
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP Yes (ISP via JTAG)
Dedicated Input Pins 4 (low-skew global) —
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] —
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power QFP)
Operating Temperature Grade Industrial —
Technology CMOS EEPROM —
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
Maximum Clock Frequency — 117.6 MHz
Supply Voltage — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
Operating Temperature — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
Lifecycle Status — Obsolete (PDN0706, 2007)

Datasheets & Resources

Browse All Products Create BOM Request Quote