EPM9320RI208-20 vs EPM9320RC208-15 对比

详细并排对比 EPM9320RI208-20 出自 Intel 和 EPM9320RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320RI208-20 EPM9320RC208-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $18.95 $0.00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 —
Usable Gates 6,000 6,000
Propagation Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (VCC) 5.0 V —
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) —
Programmable Interconnect Programmable Interconnect Array (PIA) —
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP Yes (ISP via JTAG)
Dedicated Input Pins 4 (low-skew global) —
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] —
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power QFP)
Operating Temperature Grade Industrial —
Technology CMOS EEPROM —
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
最大时钟频率 — 117.6 MHz
电源电压 — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
工作温度 — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
生命周期状态 — Obsolete (PDN0706, 2007)

数据手册与资源

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