EPM9400LC84-20 - MAX 9000 CPLD 400 Macrocells 5V ISP | Altera
MPN: EPM9400LC84-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $60 | $60.00 |
| 10 | $55 | $550.00 |
| 100 | $48.5 | $4,850.00 |
| 500 | $42 | $21,000.00 |
| 1,000 | $38.5 | $38,500.00 |
Drop-in alternatives for EPM9400LC84-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9400LC84-15
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View Datasheet →EPM9400LC84-10
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EPM9320LC84-20
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View Datasheet →EPM9320LC84-10
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View Datasheet →EPM7160SLC84-15
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View Datasheet →EPM9400LC84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based |
| Macrocells | 400 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) |
| Flip-Flops | 580 |
| Maximum User I/O | 55 |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | CMOS EEPROM |
| Operating Temperature | Commercial (0C to +70C) - assumed from -20 speed grade |
| Mounting Type | Surface Mount (PLCC socket or SMT land pattern) |
EPM9400LC84-20 84-pin plcc (plastic leaded chip carrier) Pin Configuration Guide
Complete pinout information for EPM9400LC84-20 (84-pin plcc (plastic leaded chip carrier) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9400LC84-20.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9400LC84-20 is suitable for 7 applications: Peripheral Bus Interface (PCI/ISA/VME Bridging), Address Decoding and Glue Logic, State-Machine Controller, Peripheral Driver (UART/FIFO/Timer), Industrial Control Logic Replacement, Legacy System Field Replacement, Test and Measurement Equipment Interface.
Peripheral Bus Interface (PCI/ISA/VME Bridging)
The EPM9400LC84-20's 400 macrocells and 55 user I/Os make it well-suited for legacy peripheral bus bridging between PCI, ISA, and VME interfaces in industrial backplane systems. With 20 ns pin-to-pin tpd (speed grade -20) and counter frequencies up to 144 MHz, the device can decode bus addresses, generate chip selects, and arbitrate interrupts with deterministic timing - critical for real-time backplane protocols. The 5 V VCCIO tolerance matches legacy 5 V bus signaling levels, while the JTAG ISP allows field firmware updates. Place the CPLD between the bus transceivers and the local MCU/ASIC to offload glue logic and replace discrete 74-series TTL.
Recommended
Address Decoding and Glue Logic
With 400 macrocells and fast 20 ns tpd, the EPM9400LC84-20 efficiently performs address decoding, chip-select generation, and bus steering in microprocessor systems. The device's wide input gating (up to 80 product terms per macrocell in MAX architecture) handles complex address maps without external 74LS138/139 decoders, saving PCB area and improving signal integrity. The 5 V tolerance interfaces directly with 5 V microprocessors and memories, while the EEPROM-based MAX architecture provides instant-on configuration - no boot delay. This makes it ideal for legacy 8051, 68k, and x86 system designs where deterministic power-up behavior is required.
Recommended
State-Machine Controller
The EPM9400LC84-20's 580 flip-flops across 400 macrocells make it well-suited for implementing complex state machines - sequencers, protocol controllers, and timing generators - in industrial automation equipment. The deterministic 20 ns tpd ensures predictable state-transition timing regardless of internal routing, a key advantage over FPGA-based state machines. The non-volatile EEPROM configuration means the device powers up directly into the correct state, eliminating the boot delay of SRAM-based FPGAs. Quartus and MAX+PLUS II design tools provide state-machine entry with HDL or graphical encoding, supporting up to hundreds of states.
Recommended
Peripheral Driver (UART/FIFO/Timer)
The EPM9400LC84-20 implements custom UART, FIFO buffer, and timer peripherals with deterministic timing, replacing multiple discrete 16C550-style UARTs and 8254 timers in embedded designs. The 400 macrocells and 580 flip-flops allow multi-channel UART implementations (up to 4 full-duplex channels with FIFO), while the 55 I/O pins provide ample handshake and interrupt lines. The 5 V I/O tolerance matches RS-232/RS-485 transceiver signal levels, and the JTAG ISP allows in-field baud-rate or protocol updates without board rework.
Recommended
Industrial Control Logic Replacement
The EPM9400LC84-20 replaces multiple 74LS/74HC TTL glue-logic ICs in industrial PLC and process-control systems, integrating decoder, latch, multiplexer, and flip-flop functions into a single chip. With 400 macrocells and 580 flip-flops, the device can replace up to 20 equivalent TTL packages, reducing PCB area, BOM cost, and mean-time-between-failure rate. The commercial temperature range (0C to +70C) suits factory-floor enclosures, and the JTAG ISP allows last-minute logic changes during commissioning. Designers targeting IEC 61131-3 or ladder-logic emulation frequently choose MAX 9000 CPLDs for this reason.
Recommended
Legacy System Field Replacement
The EPM9400LC84-20 serves as a form-fit-function replacement for legacy MAX 9000 designs that require ongoing maintenance due to component failure or feature updates. Because the device retains the same 84-pin PLCC footprint, EEPROM non-volatile configuration, and JTAG ISP as previous-generation MAX 9000 parts, existing PCBs and Quartus/MAX+PLUS II design files remain compatible. This eliminates costly board respins and toolchain migration for industrial customers with long-life-cycle equipment (15-20 year service windows). Stock from authorized Altera distributors remains available for these maintenance programs.
Recommended
Test and Measurement Equipment Interface
The EPM9400LC84-20's combination of 55 I/O pins, 400 macrocells, and 5 V tolerance makes it valuable for interface logic in oscilloscopes, logic analyzers, and data-acquisition systems. The device can implement parallel-bus capture, trigger generation, channel multiplexing, and timing-skew compensation with deterministic 20 ns delays. JTAG ISP enables factory calibration and field firmware updates without disassembly. The 580 flip-flops handle deep FIFO buffers and parallel-data pipelining for high-speed ADC/DAC interfacing, while EEPROM non-volatility ensures instant power-up to known states - critical for safety-critical test equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM9400LC84-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9400LC84-15 | EPM9400LC84-10 | EPM9320LC84-20 | EPM9320LC84-15 | EPM9320LC84-10 | EPM7160SLC84-15 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 7000S |
| Macrocells | 400 | 400 (same) | 400 (same) | 320 (-20%) | 320 (-20%) | 320 (-20%) | 160 (-60%) |
| Pin-to-Pin tpd | 20 ns | 15 ns (faster) | 10 ns (faster) | 20 ns (same) | 15 ns (faster) | 10 ns (faster) | 15 ns (faster) |
| Max Counter Frequency | 144 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| VCCINT | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| In-System Programming | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Flip-Flops | 580 | 580 (same) | 580 (same) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Faster pin-to-pin tpd (15 ns vs 20 ns) with identical macrocell count (vs EPM9400LC84-20 vs EPM9400LC84-15)
- Highest macrocell density in MAX 9000 family (400 vs 320 in EPM9320) (vs EPM9400LC84-20 vs EPM9320LC84-20)
- Largest 84-pin PLCC MAX 9000 device with full 5 V I/O tolerance (vs EPM9400LC84-20 vs EPM7160SLC84-15)
Design Notes
The EPM9400LC84-20 requires a stable 5 V supply on VCCINT (pin VCC) and a separate 3.3 V or 5 V supply on VCCIO pins. Place 0.1 uF ceramic decoupling capacitors as close as possible to every VCC pin, with additional 10 uF bulk capacitors near the package. The MAX 9000 family has separate VCCINT (internal logic) and VCCIO (I/O drivers) planes; improper decoupling can cause JTAG ISP failures or intermittent logic errors. Estimated: at 400 macrocells fully utilized with 100 MHz toggling, ICCINT may reach 200-400 mA - verify with the MAX 9000 power calculator (AN74) before committing to your power budget.
The 84-pin PLCC package has a 1.27 mm pitch and supports both through-hole socket mounting and surface-mount land patterns. For new designs, the SMT land pattern is preferred to avoid socket inductance; for legacy maintenance, a PLCC socket (e.g., 3M 8434-21B1-RK-TF) allows device swap without rework. Route the four JTAG signals (TMS, TCK, TDO, TDI) to a 2x2 0.1-inch header with TRST tied high through 10 kohm. Provide a 4.7 kohm pull-up on TMS and TDI per the IEEE 1149.1 specification.
The MAX 9000 architecture provides predictable 20 ns pin-to-pin tpd regardless of internal routing - a key advantage over FPGAs. However, output-edge di/dt can be high: each output can drive 25 mA with 5 ns rise/fall times, generating ground bounce on shared return paths. Use a continuous ground plane beneath the PLCC footprint and isolate I/O ground returns from logic ground where possible. For high-speed designs (>50 MHz), series-terminate clock and high-fanout outputs with 33-ohm resistors near the driver pin.
Three pitfalls to avoid with the EPM9400LC84-20: (1) Do not confuse the -20 speed grade suffix with package count - '84' is the pin count and '-20' is tpd in nanoseconds. (2) Do not assume modern CPLD design tools support MAX 9000 - use Quartus II v13.0 or MAX+PLUS II (legacy); Quartus Prime does not support MAX 9000. (3) Do not exceed the 5.5 V absolute maximum on any VCCIO pin or 7 V on VCCINT - damage is permanent. Always check the Altera/Intel NRND notice before committing new designs to MAX 9000.
Compliance Information
RoHS/REACH status not specified in the provided verified web data. As a legacy Altera (now Intel) product from the MAX 9000 family introduced in the 1990s, the part may not be RoHS-compliant by default; check with the distributor or Intel for the latest lead-free and RoHS-compliant order codes. AEC-Q100 is not applicable for industrial-grade CPLDs. All compliance fields except aec_q100 marked 'unknown' due to absence of explicit data in the verified sources.
