EPM9560ARC240-10 vs EPM9560RC-15 Comparison

Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560RC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560ARC240-10

EPM9560ARC240-10 - MAX 9000 CPLD 560 Macrocells 144.9MHz | Altera

EPM9560ARC240-10 Obsolete
Altera
EPM9560RC-15

EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel

EPM9560RC-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560ARC240-10 EPM9560RC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $28.80 $30.10
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) - third generation
Usable Gates 12,000 12,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) β€”
Internal Frequency 144.9 MHz β€”
Propagation Delay (tpd) 11.4 ns β€”
Supply Voltage - Internal (VCCINT) 5.0 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) β€”
Process Technology CMOS EEPROM CMOS EEPROM
Package 240-pin PowerQuad QFP (RQFP / EAR240) 240-pin RQFP (32x32 mm)
Operating Temperature 0C to +70C (commercial) 0 C to +70 C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) β€”
Logic Family CMOS β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Logic Array Blocks (LABs) β€” 16 (40 macrocells each)
Maximum User I/O Pins β€” 191
Pin-to-Pin Delay (tPD1) β€” 15 ns
Supply Voltage (VCCINT) β€” 4.75 V to 5.25 V (5.0 V nominal)
Mounting Type β€” Surface Mount
Programming Interface β€” IEEE Std. 1149.1 JTAG (ISP)
In-System Programmability β€” Yes (5.0 V ISP via JTAG)

Datasheets & Resources

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