EPM9560ARC240-10 vs EPM9560RC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC240-10 sa pamamagitan ng Altera at EPM9560RC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560ARC240-10 EPM9560RC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) - third generation
Usable Gates 12,000 12,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz —
Propagation Delay (tpd) 11.4 ns —
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM CMOS EEPROM
Packhaging 240-pin PowerQuad QFP (RQFP / EAR240) 240-pin RQFP (32x32 mm)
Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Logic Array Blocks (LABs) — 16 (40 macrocells each)
Maximum User I/O Pins — 191
Pin-to-Pin Delay (tPD1) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
Uri ng Pagpapasok — Surface Mount
Programming Interface — IEEE Std. 1149.1 JTAG (ISP)
In-System Programmability — Yes (5.0 V ISP via JTAG)

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