EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
MPN: EPM9560RC-15 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $43.2 | $432.00 |
| 100 | $38.9 | $3,890.00 |
| 500 | $34.5 | $17,250.00 |
| 1,000 | $30.1 | $30,100.00 |
Drop-in alternatives for EPM9560RC-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM9560RC-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) |
| Maximum User I/O Pins | 191 |
| Pin-to-Pin Delay (tPD1) | 15 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) |
| Operating Temperature | 0 C to +70 C (commercial) |
| Package | 240-pin RQFP (32x32 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | Yes (5.0 V ISP via JTAG) |
EPM9560RC-15 Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 2 | I/O — General-purpose user I/O (bank 1) |
| Pin 3 | I/O — General-purpose user I/O (bank 1) |
| Pin 4 | GND — Ground |
| Pin 5 | I/O — General-purpose user I/O (bank 1) |
| Pin 6 | I/O — General-purpose user I/O (bank 1) |
| Pin 7 | I/O — General-purpose user I/O (bank 1) |
| Pin 8 | VCC — 5.0 V supply (bank 1) |
| Pin 9 | I/O — General-purpose user I/O (bank 1) |
| Pin 10 | I/O — General-purpose user I/O (bank 1) |
| Pin 60 | GND — Ground (center) |
| Pin 61 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 62 | TMS — JTAG Test Mode Select |
| Pin 63 | TCK — JTAG Test Clock |
| Pin 64 | TDO — JTAG Test Data Out |
| Pin 120 | VCC — 5.0 V supply (bank 2) |
| Pin 121 | GND — Ground (bank 2) |
| Pin 180 | I/O — General-purpose user I/O (bank 3) |
| Pin 239 | I/O — General-purpose user I/O (bank 4) |
| Pin 240 | GND — Ground (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC-15 is suitable for 6 applications: High-Pin-Count Bus Interface Bridging, Address Decoding and Chip-Select Generation, Industrial Control Glue Logic, 5V PCI Bus Interface Adapter, State Machine and Control Logic for DSP Co-Processors, Legacy System Maintenance and Field Repair.
High-Pin-Count Bus Interface Bridging
The EPM9560RC-15's 191 available user I/O pins in a 240-RQFP package make it well suited to bus bridging between legacy 5 V microprocessors, DSPs, and peripheral devices. Its 15 ns pin-to-pin delay supports synchronous bus cycles up to approximately 66 MHz, allowing the device to act as a transparent address/data multiplexer or protocol translator between asynchronous buses. The 5 V tolerant I/Os with PCI-compatible drive strength enable direct interfacing with PCI and TTL-level buses without external level shifters. Designers typically instantiate the EPM9560RC-15 as a glue-logic bridge between a 32-bit local bus and a 16-bit peripheral bus, where its 560 macrocells comfortably absorb chip-select decode trees, wait-state generators, and interrupt steering logic.
Recommended
Address Decoding and Chip-Select Generation
CPLDs excel at deterministic address decoding, and the EPM9560RC-15's 560 macrocells deliver ample capacity for generating dozens of chip-select signals from a wide microprocessor address bus. The MAX architecture's Programmable Interconnect Array (PIA) provides a fixed, predictable interconnect delay independent of logic placement, ensuring every chip-select has identical timing - critical for synchronous memory and peripheral interfaces. With 15 ns tPD1, the device can decode a 24- or 32-bit address and assert a chip-select within one memory cycle at 66 MHz operation. Typical designs use the EPM9560RC-15 to consolidate discrete 74LS138/PAL decoders into a single non-volatile, in-system programmable device, simplifying PCB layout and BOM while adding revision flexibility.
Recommended
Industrial Control Glue Logic
Industrial control systems frequently require deterministic, non-volatile logic that boots instantly without external configuration memory - a use case where the EPM9560RC-15 excels. The device's 5 V tolerant I/Os interface directly with 24 V industrial signal-conditioning front-ends after optocoupler isolation, while its 560 macrocells implement state machines for motor sequencing, safety interlocks, and PLC I/O expansion. The non-volatile EEPROM configuration means power-up behavior is identical on every cycle, eliminating FPGA-style boot delays and bitstream integrity concerns. With commercial (0 to +70 C) or industrial (-40 to +85 C with EPM9560ARI240-10) temperature grades available, the family covers factory-floor deployments. Engineers value the JTAG ISP for field firmware updates without removing the device from the PCB.
Recommended
5V PCI Bus Interface Adapter
The EPM9560RC-15's PCI-compatible I/O drivers and 5 V tolerance make it a strong candidate for legacy 5 V PCI adapter cards, where it implements target/initiator state machines, configuration space registers, and interrupt logic. The 15 ns tPD1 supports 33 MHz PCI bus operation with margin, and the 191 available I/O pins handle 32-bit multiplexed address/data plus the full PCI control signal set (FRAME, IRDY, TRDY, DEVSEL, STOP, IDSEL, etc.). The EEPROM-based configuration eliminates PCI bitstream loading sequences, simplifying BIOS/option-ROM interaction. Designers commonly use the EPM9560RC-15 to glue a custom ASIC or DSP to the PCI bus in industrial control, medical imaging, or data acquisition cards where modern PCIe is unnecessary.
Recommended
State Machine and Control Logic for DSP Co-Processors
Pairing a CPLD with a DSP offloads deterministic control tasks, freeing the DSP for signal-processing throughput. The EPM9560RC-15 implements complex state machines for sample-rate conversion, DMA handshaking, and codec interfacing while the DSP focuses on FFTs and filtering. The 560 macrocells absorb multi-channel TDM frame synchronization, and the deterministic 15 ns PIA delay ensures sample-accurate timing across all channels - critical in audio and instrumentation applications. The 240-RQFP package offers 191 I/Os for parallel data paths to multiple peripherals. JTAG ISP allows field updates to control logic independently of DSP firmware, accelerating development cycles for prototypes and low-volume products.
Recommended
Legacy System Maintenance and Field Repair
Long-lifecycle industrial, military, and medical equipment often relies on the EPM9560RC-15 for repair and refurbishment where the original design cannot be changed due to qualification or regulatory constraints. The device's mature MAX 9000 architecture means spare-part inventories, programming tools, and bitstream archives remain available, and the EEPROM configuration retains data for decades without battery backup. Engineers sourcing EPM9560RC-15 for service replacements should validate authenticity via JTAG IDCODE readback and inspect for remarking. The exposed-pad 240-RQFP package is straightforward to rework with hot-air or infrared stations, and the JTAG ISP allows in-system verification that the replacement device is functional before final assembly.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC-10 | EPM9480RC240-15 | EPM9560ARI240-10 | EPM9560ARC240-10 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 240-RQFP (32x32) | 240-RQFP (32x32) | 240-RQFP (32x32) | 240-RQFP (32x32) | 240-RQFP (32x32) |
| Macrocells | 560 | 560 | 480 (-14%) | 560 | 560 |
| Pin-to-Pin Delay (tPD1) | 15 ns | 10 ns (-33%) | 15 ns | 10 ns (-33%) | 10 ns (-33%) |
| Maximum User I/O | 191 | 191 | 175 (approx) | 191 | 191 |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) | Yes (JTAG IEEE 1149.1) |
Key Differentiators
- Highest macrocell density in the MAX 9000 family with 240-RQFP package (vs EPM9480RC240-15)
- Commercial temperature grade optimized for cost-sensitive designs (vs EPM9560ARI240-10)
- Industry-standard JTAG ISP simplifies field upgrades (vs EPM7256SQC208-10)
- 5 V native I/O eliminates level-shifters in legacy systems (vs MAX V CPLDs)
Design Notes
Estimated: the EPM9560RC-15 draws approximately 200-400 mA from its 5.0 V VCC supply at full switching activity across all 191 I/Os. Place one 100 nF X7R ceramic decoupling capacitor within 5 mm of every VCC/GND pair (the 240-RQFP exposes roughly 8-10 VCC pins distributed around the package perimeter) plus a single 10 uF tantalum or polymer bulk capacitor adjacent to the device. This decoupling network suppresses VCC sag during simultaneous I/O switching, which would otherwise corrupt ISP programming and cause functional failures at the 15 ns tPD1 timing edge.
The 240-RQFP package exposes a thermal pad on its underside that MUST be soldered to a copper pour on the PCB for reliable operation. Without this pad connection, junction temperature can rise 15-20 C above ambient at full I/O toggling. Use a via array (8-12 thermal vias, 0.3 mm drill, 0.6 mm pad) under the exposed pad connecting to an internal ground plane. At commercial temperature (0-70 C), this thermal strategy keeps the junction well below 125 C maximum even at maximum toggle activity.
Route JTAG signals (TDI, TDO, TMS, TCK) as a daisy-chain with TCK buffered if the chain exceeds 150 mm total length. Place a 4-pin 0.1-inch JTAG header on the PCB boundary with TDI on pin 1, TDO on pin 2, TMS on pin 3, TCK on pin 4. Series-terminate TCK with 33 ohm if reflections appear on long chains. Always include a pull-up (10 kohm) on TCK and TMS, and a pull-up on TDI to keep the JTAG state machine in known-good state during power-up. Without these pull-ups, the device may enter unwanted JTAG states that block ISP.
The MAX 9000 family uses 5 V EEPROM cells that require a clean VCC ramp during ISP - power-supply glitches during programming can corrupt the configuration memory and brick the device permanently. Ensure VCC monotonic ramp from 0 to 5 V within 100 ms, and avoid in-system resets or large load steps during ISP. If a corrupted configuration is suspected, attempt JTAG IDCODE readback first to verify silicon presence before re-programming. Modern Quartus Prime (post-2019) does NOT support MAX 9000 - retain legacy MAX+PLUS II 10.23 or Quartus II 9.1sp2 toolchains.
Compliance Information
MAX 9000 family predates widespread RoHS adoption; RoHS compliance status not confirmed in provided data. Parts sourced through specialty distributors should be verified for lead-free/RoHS compliance via lot-specific documentation before use in RoHS-required products.
