EPM9560RC208-15 vs EPM9560RC208-13 Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560RC208-13 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-15 | EPM9560RC208-13 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | -13 (13 ns pin-to-pin) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Device Family | — | MAX 9000 EPLD |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 20 |
| User I/O Pins | — | 208 |
| Package Code | — | RC208 |
| Propagation Delay (tPD) | — | 13 ns |
| Maximum Clock Frequency | — | 125 MHz |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Operating Temperature Range | — | 0C to +70C (commercial) |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| MSL Level | — | [DATA_NEEDED: MSL level] |