EPM9560RC208-15 vs EPM9560RC208-13 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-15 sa pamamagitan ng Altera at EPM9560RC208-13 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC208-15 EPM9560RC208-13
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 gates 12,000
Macro Cells 560 macro cells —
Pin-to-Pin Delay 15 ns —
Counter Speed 117.6 MHz —
Volte ng Pagbibigay 5.0 V 5.0 V
Configuration Technology EEPROM (non-volatile) EEPROM (non-volatile)
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
Packhaging 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Number of I/O Pins [DATA_NEEDED: number of I/O pins] —
Logic Array Blocks [DATA_NEEDED: number of logic array blocks] —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -15 (15 ns pin-to-pin) -13 (13 ns pin-to-pin)
Architecture Third-generation Multiple Array MatriX (MAX) —
Device Family — MAX 9000 EPLD
Macrocells — 560
Logic Array Blocks (LABs) — 20
User I/O Pins — 208
Package Code — RC208
Propagation Delay (tPD) — 13 ns
Maksimum na Taktiko ng Oras — 125 MHz
Programming Interface — IEEE 1149.1 JTAG
Hanay ng Temperature na Operasyon — 0C to +70C (commercial)
Lead-Free Status — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL level]

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