EPM9560RC208-15 vs EPM9560RC208-16 Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560RC208-16 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
EPM9560RC208-16 NrndSpecification Comparison
| Parameter | EPM9560RC208-15 | EPM9560RC208-16 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 gates | 12,000 (typical) |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Supply Voltage | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin Power Quad Flat Pack (RQFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temperature grade] |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -15 (15 ns pin-to-pin) | -16 |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Logic Elements / Macrocells | — | 560 macrocells |
| Typical Gates | — | 12,000 gates |
| Pin-to-Pin Delay (tPD) | — | 16 ns |
| Maximum Internal Frequency (fMAX) | — | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V |
| User I/O Pins | — | 416 |
| Process Technology | — | 0.35 µm CMOS EEPROM |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |