EPM9560RC208-15 vs EPM9560RC208-16 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-15 sa pamamagitan ng Altera at EPM9560RC208-16 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
EPM9560RC208-16 NrndPagsanggunian na paghahambing
| Parametro | EPM9560RC208-15 | EPM9560RC208-16 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 gates | 12,000 (typical) |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin Power Quad Flat Pack (RQFP) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temperature grade] |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -15 (15 ns pin-to-pin) | -16 |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Logic Elements / Macrocells | — | 560 macrocells |
| Typical Gates | — | 12,000 gates |
| Pin-to-Pin Delay (tPD) | — | 16 ns |
| Maximum Internal Frequency (fMAX) | — | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V |
| User I/O Pins | — | 416 |
| Process Technology | — | 0.35 µm CMOS EEPROM |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |