EPM9560RC208-17 vs EPM9560RC208-18 Comparison
Detailed side-by-side comparison of EPM9560RC208-17 by Altera and EPM9560RC208-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-17 | EPM9560RC208-18 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | End of Life |
| Family | MAX 9000 | — |
| Product Type | CPLD (EPLD, in-system programmable) | — |
| Usable Gates | 12,000 | 12,000 gates |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 17 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | — |
| Supply Voltage (VCC) | 5 V | — |
| Package | 208-pin RQFP (RC208) | 208-pin RQFP (Power Quad Flat Pack) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Device Family | — | MAX 9000 (EPM9560) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 560 macrocells |
| Propagation Delay (tPD) | — | 18 ns (speed grade -18) |
| Maximum Operating Frequency | — | 117.6 MHz (family -15 grade reference) |
| Supply Voltage | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| User I/O Lines | — | 149 I/O lines |
| Flip-Flops | — | 772 flip-flops |
| Package JESD-30 Code | — | S-PQFP-G208 |
| Configuration Memory | — | EEPROM (non-volatile, no external config PROM) |
| Technology | — | CMOS |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | — | EOL / mature (per Altera product discontinuance notice) |