EPM9560RC240-10 vs EPM9560RC240-15N Comparison

Detailed side-by-side comparison of EPM9560RC240-10 by Altera and EPM9560RC240-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC240-10 EPM9560RC240-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Device Type Complex Programmable Logic Device (CPLD) —
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Usable Gates 12,000 gates 12,000
Macro Cells 560 —
Logic Array Blocks (LABs) 12 35
Maximum System Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay 10 ns —
Supply Voltage 5 V 5.0 V
Technology CMOS EEPROM —
Package 240-pin RQFP (PowerQuad) RQFP-240 (240-pin Plastic Quad Flat Pack)
User I/O Pins 192 —
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0C to +70C (Commercial)
Moisture Sensitivity Level (MSL) 3 (168 Hours) —
RoHS Status ROHS3 Compliant [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Configuration Memory Non-volatile EEPROM (instant-on) —
Manufacturer Standard Lead Time 1-7 Days (distributor stock) —
Series — MAX 9000
Macrocells — 560
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

Datasheets & Resources

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