EPM9560RC240-10 vs EPM9560RC240-15N Comparación
Comparación detallada lado a lado de EPM9560RC240-10 por Altera y EPM9560RC240-15N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC240-10 | EPM9560RC240-15N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $27,85 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000 (third-generation Multiple Array MatriX) |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 12 | 35 |
| Maximum System Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Tensión de alimentación | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Encapsulado | 240-pin RQFP (PowerQuad) | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| User I/O Pins | 192 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Estado RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Configuration Memory | Non-volatile EEPROM (instant-on) | — |
| Manufacturer Standard Lead Time | 1-7 Days (distributor stock) | — |
| Series | — | MAX 9000 |
| Macrocells | — | 560 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Logic Family | — | CMOS (EEPROM-based) |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |