EPM9560RC240-10 vs EPM9560RC240-15N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-10 sa pamamagitan ng Altera at EPM9560RC240-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC240-10 EPM9560RC240-15N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Type Complex Programmable Logic Device (CPLD) —
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Usable Gates 12,000 gates 12,000
Macro Cells 560 —
Logic Array Blocks (LABs) 12 35
Maximum System Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay 10 ns —
Volte ng Pagbibigay 5 V 5.0 V
Technology CMOS EEPROM —
Packhaging 240-pin RQFP (PowerQuad) RQFP-240 (240-pin Plastic Quad Flat Pack)
User I/O Pins 192 —
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (Commercial)
Level ng Sensitivity sa Asid ng Moisture (MSL) 3 (168 Hours) —
Tindminan RoHS ROHS3 Compliant [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Configuration Memory Non-volatile EEPROM (instant-on) —
Manufacturer Standard Lead Time 1-7 Days (distributor stock) —
Series — MAX 9000
Macrocells — 560
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

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