EPM9560RC240-10 vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RC240-10 出自 Altera 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-10 EPM9560RC240-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.00 $27.85
Device Type Complex Programmable Logic Device (CPLD) —
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Usable Gates 12,000 gates 12,000
Macro Cells 560 —
Logic Array Blocks (LABs) 12 35
Maximum System Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay 10 ns —
电源电压 5 V 5.0 V
Technology CMOS EEPROM —
封装 240-pin RQFP (PowerQuad) RQFP-240 (240-pin Plastic Quad Flat Pack)
User I/O Pins 192 —
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) 0C to +70C (Commercial)
湿敏等级(MSL) 3 (168 Hours) —
RoHS 状态 ROHS3 Compliant [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Configuration Memory Non-volatile EEPROM (instant-on) —
Manufacturer Standard Lead Time 1-7 Days (distributor stock) —
Series — MAX 9000
Macrocells — 560
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

数据手册与资源

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