EPM9560RC240-15W vs EPM9560RC240-15N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC240-15W disebabkan oleh Altera dan EPM9560RC240-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560RC240-15W EPM9560RC240-15N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Device Type Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 12,000
Macrocells 560 560
User I/O Pins 191 —
Pin-to-Pin Delay 15 ns —
Internal Frequency 117.6 MHz —
Tegangan Pemberi Arus 4.75 V to 5.25 V 5.0 V
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (ISP via JTAG) —
Kemasan 240-pin RQFP (PowerQuad) with exposed pad RQFP-240 (240-pin Plastic Quad Flat Pack)
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi 0C to +70C (commercial) 0C to +70C (Commercial)
Logic Family CMOS CMOS (EEPROM-based)
Bilangan Pin 240 —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Aras MSL [DATA_NEEDED: MSL level] —
Series — MAX 9000
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga