EPM9560RI208-10 - 12K-Gate MAX 9000 CPLD, 10ns, 208-Pin RQFP
MPN: EPM9560RI208-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $86.5 | $865.00 |
| 100 | $78.2 | $7,820.00 |
| 250 | $72.4 | $18,100.00 |
| 500 | $67.8 | $33,900.00 |
Drop-in alternatives for EPM9560RI208-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RI208-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$20.1 / Unit
View Datasheet →EPM9560RI208-20
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$21.1 / Unit
View Datasheet →EPM9560ARI208-10
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View Datasheet →EPM7256SRI208-10
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$27.2 / Unit
View Datasheet →EPM9320RI208-20
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$18.95 / Unit
View Datasheet →EPM9560RI208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| User I/O Pins | 212 (typical for 208-RQFP package) |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 °C to +85 °C (Industrial) |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP |
| Configuration Memory | EEPROM, 100 erase/program cycles |
| RoHS Status | ROHS3 Compliant |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Lead Time | 1-7 days (per fpgalink listing) |
EPM9560RI208-10 208-pin rqfp (power quad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RI208-10 (208-pin rqfp (power quad flat pack) package) with 212 (typical for 208-RQFP package) pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RI208-10.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 (typical for 208-RQFP package) pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-10 is suitable for 6 applications: 5 V PCI Bus Interface Glue Logic, Embedded Bus Address Decoding & Wait-State Generation, Industrial Motor Control State Machines, Legacy Telecommunications Backplane Controllers, Test & Measurement Instrument Front-Ends, Military/Aerospace Legacy Avionics Interfaces.
5 V PCI Bus Interface Glue Logic
The EPM9560RI208-10's 5.0 V TTL-compatible I/O banks and 10 ns tPD make it a strong fit for PCI bus interface glue logic on legacy motherboards and add-in cards. It can implement target/initiator state machines, address decoding, command-handling, and wait-state generation in a single non-volatile device that boots instantly without external flash. With 560 macrocells and 212 user I/Os, the part can handle full 32-bit/33 MHz PCI decoder/arbiter logic. Unlike SRAM-based FPGAs, the EEPROM-backed configuration means no configuration-PROM is required and there is no boot latency, critical for systems that must respond to bus enumeration within the PCI spec's 2^15 clock budget.
Recommended
Embedded Bus Address Decoding & Wait-State Generation
The EPM9560RI208-10 excels at 68k, 8051, and x86 embedded-system glue logic, where it provides address decoding, chip-select generation, and programmable wait-state insertion between CPU and SRAM/ROM/Peripheral banks. The 10 ns tPD is fast enough to insert a single wait state on a 50 MHz bus while still meeting CPU-to-memory timing. With 560 macrocells, designers can implement a full address decoder plus multiple peripheral chip selects in one device. The non-volatile EEPROM configuration eliminates boot ROM requirements common to SRAM-FPGA designs.
Recommended
Industrial Motor Control State Machines
Industrial motor-control and process-control boards commonly deploy the EPM9560RI208-10 for deterministic PWM generation, fault-interrupt handling, and stepper/servo sequencer logic. Its industrial -40 °C to +85 °C operating range suits factory-floor environments, while the 10 ns tPD allows closed-loop control loops well under 1 µs. The 5 V I/O tolerance interfaces directly to legacy gate drivers and 24 V optocoupler inputs through resistive dividers. Engineers pair this CPLD with a microcontroller to offload time-critical control from the MCU, freeing CPU cycles for communication stacks.
Recommended
Legacy Telecommunications Backplane Controllers
Telecommunications backplanes in legacy T1/E1, SDH/SONET, and central-office switching equipment rely on 5 V CPLDs for bus arbitration, framing, and alarm-collection logic - exactly the role the EPM9560RI208-10 was designed for. Its instant-on EEPROM configuration means the system is operational within milliseconds of power-up, critical for telecom availability targets. The 208-RQFP package provides the mechanical robustness needed for backplane insertion, and the JTAG boundary-scan interface simplifies board-test fixtures for high-density backplane assemblies.
Recommended
Test & Measurement Instrument Front-Ends
Bench-top oscilloscopes, logic analyzers, and protocol testers often use the EPM9560RI208-10 to implement front-panel multiplexing, trigger routing, and channel-switching matrices. The deterministic 10 ns timing and 144 MHz counter frequency allow precise trigger-arming logic, while the 560 macrocells handle complex pattern-detection state machines. The 208-RQFP package is large enough to route high-impedance analog front-end signals around digital switching noise, an important consideration in mixed-signal test instruments. JTAG boundary-scan simplifies board bring-up and rework on densely populated test-instrument PCBs.
Recommended
Military/Aerospace Legacy Avionics Interfaces
The EPM9560RI208-10's industrial temperature range and 5 V tolerance have made it a long-standing choice for legacy military and avionics interface cards such as MIL-STD-1553 bridges, ARINC 429 receivers, and discrete I/O concentrators. The instant-on EEPROM configuration is preferred over SRAM FPGAs for safety-critical applications where configuration-bit errors are unacceptable. The 208-RQFP ceramic-windowed package variant supports UV erasure for prototype and radiation-tolerant builds, although the standard plastic RQFP is more common in commercial-off-the-shelf subsystems.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-15 | EPM9560RI208-20 | EPM9560ARI208-10 | EPM7256SRI208-10 | EPM9320RI208-20 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 208-RQFP | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same | 208-RQFP - same |
| Family | MAX 9000 | MAX 9000 - same | MAX 9000 - same | MAX 9000 - same | MAX 7000S | MAX 9000 |
| Macrocells | 560 | 560 | 560 | 560 | 256 (-54%) | 320 (-43%) |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns | 20 ns | 10 ns | 10 ns | 20 ns |
| Maximum Counter Frequency | 144 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 144 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V (with 3.3 V multi-volt I/O) | 5.0 V |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
| Lifecycle Status | NRND | NRND | NRND (last buy per DigiKey listing) | NRND | NRND | NRND |
Key Differentiators
- Highest-density 5 V CPLD in 208-RQFP package (vs EPM7256SRI208-10)
- Fastest speed grade in 208-RQFP MAX 9000 family (vs EPM9560RI208-20)
- Same-family 5 V operation with 212 user I/Os (vs MAX V 5M570ZT100)
Design Notes
The EPM9560RI208-10 operates from a single 5.0 V VCCINT supply; the I/O banks are 5 V TTL-compatible but not 5 V tolerant for 3.3 V inputs - direct connection to 3.3 V logic can damage inputs over time. Use external bus switches (e.g., 74CBTD3384 or SN74CB3T3384) or resistor dividers when interfacing to 3.3 V devices. Decoupling: place one 0.1 µF ceramic per VCC pin pair and a single bulk 10 µF tantalum at the supply entry, per MAX 9000 datasheet power-supply recommendations.
Estimated: at 5.0 V VCCINT, 560 macrocells switching at full internal frequency (~144 MHz) draws approximately 250-300 mA Icc, dissipating 1.25-1.5 W in the 208-RQFP package. The RQFP-208 has theta_JA of roughly 35-40 °C/W on a standard JEDEC 4-layer test board, giving a junction temperature rise of 44-60 °C above ambient. For natural-convection designs, derate VCCINT to 4.75 V at 85 °C ambient or add a small clip-on heatsink. Estimated input values: 560 macrocells, 144 MHz, 5.0 V, 35 °C/W θJA.
The 208-pin RQFP has a 0.5 mm lead pitch and a large 28×28 mm body. Provide at least 4 mm of copper-pour keep-out around the package for rework, and use NSMD (non-solder-mask-defined) pads with 0.15 mm copper-to-mask clearance for reliable fine-pitch assembly. Route all four dedicated global-clock pins (GCLK1-GCLK4) on the inner PCB layers with ground-plane shielding to control skew. The exposed-pad variants of the MAX family do not exist for this package; thermal dissipation is through peripheral leads only.
Pitfall 1: newer Quartus versions (14.0+) do not include MAX 9000 device support out of the box - install the legacy MAX 9000 device files or use MAX+PLUS II 10.x. Pitfall 2: the 208-RQFP pinout differs from the 240-RQFP used on larger MAX 9000 devices; never assume pin-compatibility between packages. Pitfall 3: PCI compliance requires 5 V signaling levels; the part's 5 V I/O supports this directly. Pitfall 4: the EEPROM configuration has only 100 erase/program cycles minimum - do not use the ISP interface as a debugging scratch area.
Route the four global clocks (GCLK1-GCLK4) with matched length (within 200 mils of each other) and a continuous ground reference plane beneath. Use 33 Ω series-termination resistors on clock outputs driving long traces or backplane connectors. The MAX 9000 has a programmable slew-rate control on each I/O pin - enable slow slew rate on switching I/Os near analog or RF sections to reduce ground bounce by approximately 50 %. Reference: MAX 9000 datasheet, Application Note 75 (Altera).
Compliance Information
ROHS3 Compliant per fpgalink product detail page. REACH and conflict-minerals status not stated in available data. Not AEC-Q100 qualified (consumer/industrial use).
