EPM9560WC208-20C vs EPM9560WI208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208-20C by Altera and EPM9560WI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-20C | EPM9560WI208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | MAX 9000 (EE PLD) | MAX 9000 |
| Series | EPM9560 | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | 16 |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Clock Frequency | [DATA_NEEDED: fMAX value not in verified data] | — |
| Process Technology | CMOS, Electrically Erasable | 0.35 micron CMOS EEPROM |
| Supply Voltage | 3.3 V or 5 V (configurable I/O) | — |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | — |
| Pin Count | 208 | — |
| Programming Interface | JTAG BST (in-system programmable) | — |
| Operating Temperature Grade | Commercial (C suffix) | Industrial |
| Mounting Type | Surface Mount (Ceramic QFP) | Surface Mount |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | — |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Device Type | — | EE PLD / Complex Programmable Logic Device (CPLD) |
| Macrocells / Logic Cells | — | 560 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 23.6 ns |
| Speed Grade | — | -20 |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |
| Package Type | — | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| Package Code | — | QFP |
| Package Shape | — | Square |
| Design Tools | — | MAX+PLUS II, Quartus |
| Compliance | — | [DATA_NEEDED: RoHS status] |