RTAX2000D-CQ352B - 2M-Gate Rad-Tolerant FPGA, CQFP-352 | Microchip
MPN: RTAX2000D-CQ352B ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4200 | $4,200.00 |
| 10 | $3980 | $39,800.00 |
| 100 | $3650 | $365,000.00 |
| 500 | $3350 | $1,675,000.00 |
| 1,000 | $3100 | $3,100,000.00 |
Drop-in alternatives for RTAX2000D-CQ352B — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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RTAX2000D-CQ352E
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View Datasheet →RTAX2000D-CQ352V
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$2560 / Unit
View Datasheet →RTAX2000D-1CQ352V
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$3950 / Unit
View Datasheet →RTAX2000DL-CQ352B
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View Datasheet →RTAX2000DL-1CQ352E
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$2300 / Unit
View Datasheet →RTAX4000D-CQ352B
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View Datasheet →RTAX2000D-CQ352B Maximum Ratings & Electrical Characteristics
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Equivalent System Gates | 2000000 |
| Logic Cells | 29568 |
| CLBs | 19712 |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) |
| Process Technology | CMOS antifuse |
| Configuration Type | One-time programmable antifuse, live at power-up |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic |
| Clocking Features | Segmentable clocks, chip-wide highway routing |
| Arithmetic Support | Carry logic |
| Package | CQFP-352 ceramic quad flat pack |
| Screening / Speed Grade | B (burn-in screening); D suffix = tighter ICCA limits at 125C final test |
| Mounting Type | Surface Mount |
| Application Domain | Space-flight systems |
| Radiation Tolerance | Radiation-tolerant (TID/SEE per family datasheet) |
RTAX2000D-CQ352B cqfp-352 ceramic quad flat pack Pin Configuration Guide
Complete pinout information for RTAX2000D-CQ352B (cqfp-352 ceramic quad flat pack package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for RTAX2000D-CQ352B.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
RTAX2000D-CQ352B is suitable for 6 applications: Satellite Payload Data Processing, Spacecraft Bus Command and Telemetry, Radiation-Hardened Reconfigurable Computing Modules, Star Tracker and Imager Interface Logic, Launcher and Avionics Interface Bridging, Prototype-to-Flight Migration Flow.
Satellite Payload Data Processing
The RTAX2000D-CQ352B fits satellite payload processing because its 2,000,000 equivalent gates and 29,568 logic cells absorb sensor formatting, packetization, and front-end compression logic in a single live-at-power-up device. The antifuse fabric has no configuration memory to upset under heavy-ion flux, eliminating the SEE-driven reconfiguration loops that burden SRAM FPGAs, while embedded SRAM blocks with FIFO control handle burst buffering between high-rate detectors and downlink encoders. In a typical chain the FPGA sits between the payload sensor and a spaceWire or LVDS formatter, with 1.5V core and banked I/O rails; the one-time-programmable fabric adds no switching-configuration overhead, but designers must budget the fixed logic partition carefully since the antifuse cannot be rewritten after flight-unit programming.
Recommended
Spacecraft Bus Command and Telemetry
Spacecraft bus controllers benefit from the RTAX2000D-CQ352B because its D-level die screening (tighter ICCA limits at 125C final electrical test) and B burn-in screening satisfy mission assurance requirements for the highest-reliability bus electronics. With 19,712 CLBs the device integrates telemetry acquisition, command decoding, and housekeeping state machines that would otherwise require several rad-hard ASICs, and its segmentable clock tree supports independent timing domains for the processor interface and low-rate telemetry peripherals. Placed between an on-board computer and MIL-STD-1553 or SpaceWire interfaces, it delivers deterministic, single-chip operation; the trade-off is one-time programmability, so flight software-controlled flexibility must live outside the FPGA.
Recommended
Radiation-Hardened Reconfigurable Computing Modules
For onboard science data reduction, the RTAX2000D-CQ352B provides 2,000,000 gates of antifuse logic whose interconnect is immune to configuration single-event upsets, a decisive property for compute modules that must run unattended for years. Carry logic accelerates fixed-point FFT, convolution, and error-correction chains, while chip-wide highway routing distributes wide data paths across the 29,568-cell fabric with predictable timing. The device is mounted on a heritage avionics board between an ADC front end and memory controllers, with the 1.5V core fed from a rad-tolerant point-of-load regulator; because the antifuse is programmed once, algorithm updates are handled at the system level via multiple programmed flight spares rather than in-orbit reconfiguration.
Recommended
Star Tracker and Imager Interface Logic
Star trackers and scientific imagers require deterministic, low-noise timing and high-bandwidth readout channels, which the RTAX2000D-CQ352B supplies with its segmentable clocks and 2,000,000-gate capacity for CCD/CMOS sequencer, correlated double sampling support, and centroid computation logic. The antifuse architecture introduces no configuration-cell switching noise, helpful for the sensitive analog front ends adjacent to the digital core, and the CQFP-352 ceramic package supports the thermal and outgassing requirements of optical payloads. The FPGA typically clocks the sensor, sequences exposure, and pre-processes star centroids before handing coordinates to the attitude computer; designers should partition timing-critical centroid paths early since the one-time-programmable fabric does not permit later timing closure iterations on flight hardware.
Recommended
Launcher and Avionics Interface Bridging
Launch-vehicle avionics frequently mix legacy bus standards with modern processors, and the RTAX2000D-CQ352B bridges them with 19,712 CLBs of glue logic, embedded SRAM FIFOs for rate decoupling, and I/O banks configurable to the required interface voltages. Its D-suffix screening and B burn-in align with launcher mission assurance flow, and the live-at-power-up antifuse configuration means interface logic is functional the instant units are energized during Range safety checks, with no configuration load time. The device typically sits between a flight computer and 1553, ARINC, or discretes interfaces; because antifuse devices cannot be reprogrammed after screening, teams maintain programmed flight spares and verify netlist parity through Microchip Libero SoC release control.
Recommended
Prototype-to-Flight Migration Flow
The RTAX2000D-CQ352B is designed for a low-risk prototype-to-flight methodology: because the RTAX architecture derives from the commercial Axcelerator family, engineers validate RTL on reprogrammable Axcelerator devices using a footprint-compatible adaptor board plus an EDIF netlist and pinout converter, exactly as described in the RTAX-S/SL datasheet and the application note Prototyping for RTAX-S and RTAX-SL Devices. Only after timing closure and functional sign-off is the one-time-programmable antifuse flight device programmed, eliminating expensive burn errors. This page lists drop-in CQFP-352 family members (RTAX2000D E/V grades, DL low-power variants, and RTAX4000D density upgrades) so the final die choice can be deferred until after prototype results, keeping a single PCB layout across all options.
Recommended
Recommended Products Summary
Engineering reference data for RTAX2000D-CQ352B — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | RTAX2000D-CQ352E | RTAX2000DL-CQ352B | RTAX4000D-CQ352B |
|---|---|---|---|---|
| Package | CQFP-352 | CQFP-352 - same | CQFP-352 - same | CQFP-352 - same |
| Brand | Microsemi (Microchip) | Microsemi (Microchip) | Microsemi (Microchip) | Microsemi (Microchip) |
| Equivalent System Gates | 2,000,000 | 2,000,000 | 2,000,000 | 4,000,000 |
| Logic Cells | 29,568 | 29,568 | 29,568 | [DATA_NEEDED] |
| Core Voltage | 1.5 V nominal | 1.5 V nominal | 1.5 V nominal | 1.5 V nominal |
| Screening / Suffix | D, B burn-in | D, E grade | DL, B burn-in | D, B burn-in |
| Configuration | Antifuse OTP, live at power-up | Antifuse OTP, live at power-up | Antifuse OTP, live at power-up | Antifuse OTP, live at power-up |
| Relative Static Power | Standard D die | Same as this product | Lower (L low-power variant) | Higher (larger die) |
Key Differentiators
- Highest-reliability screening in the 2M-gate family (vs RTAX2000D-CQ352E)
- Lower static power than the density upgrade (vs RTAX4000D-CQ352B)
- Full-speed die versus speed grade 1 (vs RTAX2000D-1CQ352V)
Design Notes
The RTAX2000D-CQ352B is one-time programmable: once antifuses are burned, the configuration can never be changed. Complete full timing closure and functional verification in Libero SoC, and validate on a commercial Axcelerator prototype using the footprint-compatible adaptor board and EDIF netlist/pinout converter flow per the manufacturer datasheet, before programming any flight device. Maintain configuration-file version control and programmed flight spares for every mission lot.
Design the 1.5V core rail to hold 1.425V to 1.575V under all load and radiation-related degradation conditions. The D-suffix die is screened to tighter ICCA limits at 125C, which improves standby-current predictability, but transient core current during carry-chain switching still requires adequate decoupling on all VCC pins of the CQFP-352. Verify I/O bank voltages against the datasheet bank tables; mixed-voltage banks must be assigned before pin lock since antifuse programming fixes them permanently.
The CQFP-352 ceramic package has leads on all four sides; use a land pattern per the mechanical drawing in the family datasheet and support the leads with solder columns where thermal cycling life is a concern, as recommended for RTAX ceramic packages. Provide a solid ground plane under the device, place 0.1uF decoupling at each supply pin group, and keep high-speed LVDS or SpaceWire pairs length-matched from the CQFP through the board connector to preserve signal integrity.
Compliance Information
Aerospace ceramic CQFP package; environmental compliance data not stated in provided web data. Consult Microchip product page for RoHS/REACH declarations.
