1EDN7550BXTSA1 vs 2EDN7524GXTMA1 Vergleich
Detaillierter Direktvergleich von 1EDN7550BXTSA1 von Infineon und 2EDN7524GXTMA1 von Infineon. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Infineon
1EDN7550BXTSA1 - 4A/8A Single-Channel Gate Driver, SOT-23-6 | Infineon
1EDN7550BXTSA1 ✓ AktivInfineon
2EDN7524GXTMA1 - 5A Dual Low-Side Gate Driver for MOSFET/GaN | Infineon
2EDN7524GXTMA1 ✓ AktivSpezifikationsvergleich
| Parameter | 1EDN7550BXTSA1 | 2EDN7524GXTMA1 |
|---|---|---|
| Marke | Infineon | Infineon |
| Kategorie | Power MOSFET Drivers | Power MOSFET Drivers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,59 | $0,82 |
| Driver Configuration | Single-channel, high-side / low-side | — |
| Input Type | Non-inverting, truly differential | — |
| Peak Source Current | 4 A | — |
| Peak Sink Current | 8 A | — |
| Supply Voltage (VDD max) | 84 V | — |
| Minimum Input Pulse Width | 29 ns | — |
| Propagation Delay (typ.) | [DATA_NEEDED: propagation delay value] | — |
| Input Common-Mode Range | Up to 150 V | — |
| Channel-to-Channel Matching | 1.0 ns typ. | — |
| Internal Regulator | 4.7 V on input side | — |
| Logic Input Compatibility | TTL / CMOS | — |
| Under-Voltage Lockout (UVLO) | Yes | — |
| Betriebs-Sperrschichttemperatur | -40 °C to +150 °C | — |
| Gehäuse | PG-SOT23-6 (SOT-23-6) | PG-WSON-8-1 (3 mm x 3 mm) with exposed thermal pad |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| RoHS-Status | Compliant | Compliant |
| Product Type | — | Low-side gate driver IC |
| Number of Channels | — | 2 (dual) |
| Drive Current (Source/Sink) | — | 5 A peak |
| Input Logic | — | Non-inverting, TTL / 3.3 V CMOS-compatible |
| Input Voltage Tolerance | — | -10 V to +20 V on logic pins |
| Supply Voltage (VCC) | — | 4.5 V to 20 V [DATA_NEEDED: exact range] |
| Propagation Delay | — | 20 ns typical [DATA_NEEDED: exact figure] |
| Channel-to-Channel Delay Matching | — | 1 ns |
| Anstiegszeit | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Abfallzeit | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Output Stage | — | Rail-to-rail, separate source/sink |
| UVLO Protection | — | Yes |
| Betriebstemperatur | — | -40 C to +125 C |
| Target Devices | — | Standard MOSFETs, superjunction MOSFETs, GaN HEMTs |