CDK8307CILP64 vs CDK8307AILP64 Vergleich

Detaillierter Direktvergleich von CDK8307CILP64 von MaxLinear und CDK8307AILP64 von MaxLinear. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter CDK8307CILP64 CDK8307AILP64
Marke MaxLinear MaxLinear
Kategorie ADC/DAC ADC/DAC
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $11,95 $18,45
Auflösung 12/13-bit (selectable) 12/13-bit (selectable)
Sample Rate 65 MSPS maximum (20/40/50/65 MSPS grades) —
Number of Channels 8 (simultaneous sampling) 8 (simultaneous sampling)
Digital Output Interface Serial LVDS —
Input Type Differential analog inputs —
Reference Internal (integrated bandgap) Internal reference (integrated)
Control Interface SPI-compatible serial Serial programming interface (SPI-style)
Gehäuse 64-pin LQFP (LP64) 64-pin QFN (ILP64)
Architecture Proprietary pipeline ADC Pipelined ADC with proprietary core
Power Profile Ultra-low power (per-channel) —
Betriebstemperaturbereich [DATA_NEEDED: operating temperature range] [DATA_NEEDED: temperature range]
Supply Voltage (AVDD) [DATA_NEEDED: AVDD nominal] —
Supply Voltage (DRVDD/LVDS) [DATA_NEEDED: DRVDD nominal] —
ENOB [DATA_NEEDED: effective number of bits] —
SNR [DATA_NEEDED: signal-to-noise ratio] —
SFDR [DATA_NEEDED: spurious-free dynamic range] —
RoHS-Status Compliant (per MaxLinear product page) Compliant
Montageart Surface Mount Surface Mount
Sample Rate Range — 20 / 40 / 50 / 65 / 80 MSPS
Output Interface — Serial LVDS
Versorgungsspannung — [DATA_NEEDED: supply voltage]
Power Dissipation (Typ) — Ultra-low power (per-channel shutdown)
Shutdown Modes — Per-channel + full-chip idle (via external pin)
FPGA Compatibility — Designed to interface with major FPGA vendors
Original Brand — Cadeka / Exar (now MaxLinear)

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