CDK8307CILP64 vs CDK8307AILP64 对比
详细并排对比 CDK8307CILP64 出自 MaxLinear 和 CDK8307AILP64 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | CDK8307CILP64 | CDK8307AILP64 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 分类 | ADC/DAC | ADC/DAC |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $11.95 | $18.45 |
| 分辨率 | 12/13-bit (selectable) | 12/13-bit (selectable) |
| Sample Rate | 65 MSPS maximum (20/40/50/65 MSPS grades) | — |
| Number of Channels | 8 (simultaneous sampling) | 8 (simultaneous sampling) |
| Digital Output Interface | Serial LVDS | — |
| Input Type | Differential analog inputs | — |
| Reference | Internal (integrated bandgap) | Internal reference (integrated) |
| Control Interface | SPI-compatible serial | Serial programming interface (SPI-style) |
| 封装 | 64-pin LQFP (LP64) | 64-pin QFN (ILP64) |
| Architecture | Proprietary pipeline ADC | Pipelined ADC with proprietary core |
| Power Profile | Ultra-low power (per-channel) | — |
| 工作温度范围 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature range] |
| Supply Voltage (AVDD) | [DATA_NEEDED: AVDD nominal] | — |
| Supply Voltage (DRVDD/LVDS) | [DATA_NEEDED: DRVDD nominal] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| SNR | [DATA_NEEDED: signal-to-noise ratio] | — |
| SFDR | [DATA_NEEDED: spurious-free dynamic range] | — |
| RoHS 状态 | Compliant (per MaxLinear product page) | Compliant |
| 安装类型 | Surface Mount | Surface Mount |
| Sample Rate Range | — | 20 / 40 / 50 / 65 / 80 MSPS |
| Output Interface | — | Serial LVDS |
| 电源电压 | — | [DATA_NEEDED: supply voltage] |
| Power Dissipation (Typ) | — | Ultra-low power (per-channel shutdown) |
| Shutdown Modes | — | Per-channel + full-chip idle (via external pin) |
| FPGA Compatibility | — | Designed to interface with major FPGA vendors |
| Original Brand | — | Cadeka / Exar (now MaxLinear) |