EP1810GC-35 vs EP1810LC-30 Vergleich
Detaillierter Direktvergleich von EP1810GC-35 von Altera und EP1810LC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1810GC-35 | EP1810LC-30 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $177,12 | $9,95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | CMOS, low-power (LC) |
| Gehäuse | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Anzahl der Pins | 68 | 68 |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | 5 V (typical) |
| Montageart | Through Hole | — |
| RoHS-Status | Not applicable (legacy ceramic package) | unknown (legacy ceramic package) |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |