EP1810GC-35 vs EP1810LC-30 비교
다음의 상세 나란히 비교: EP1810GC-35 제조: Altera 및 EP1810LC-30 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810GC-35 | EP1810LC-30 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $177.12 | $9.95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | CMOS, low-power (LC) |
| 패키지 | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| 핀 수 | 68 | 68 |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| 공급 전압 | [DATA_NEEDED: VCC range] | 5 V (typical) |
| 실장 유형 | Through Hole | — |
| RoHS 상태 | Not applicable (legacy ceramic package) | unknown (legacy ceramic package) |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |