EP1810JI-35 vs EP1810LC-25 Vergleich

Detaillierter Direktvergleich von EP1810JI-35 von Intel und EP1810LC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JI-35 EP1810LC-25
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,60 $8,40
Device Family Classic EPLD —
Macrocells 48 48
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 12
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 —
Gehäuse 28-pin JLCC (J-leaded ceramic, windowed) 68-pin JLCC (J-leaded ceramic chip carrier)
Process Technology CMOS EPROM (UV-erasable) —
Betriebstemperatur -40C to +85C (Industrial) [DATA_NEEDED: temperature grade for LC package]
Versorgungsspannung 5 V (typical classic EPLD) —
Programmability UV-erase, windowed for lab reprogram —
Montageart Through-Hole (J-lead) Surface Mount
RoHS-Status [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Interface JEDEC fuse file via legacy programmer —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Lebenszyklusstatus — Obsolete (legacy Altera Classic family)

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