EP1810JI-35 vs EP1810LC-25 比較
詳細な並列比較: EP1810JI-35 メーカー: Intel および EP1810LC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810JI-35 | EP1810LC-25 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.60 | $8.40 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| パッケージ | 28-pin JLCC (J-leaded ceramic, windowed) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 動作温度 | -40C to +85C (Industrial) | [DATA_NEEDED: temperature grade for LC package] |
| 電源電圧 | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 実装タイプ | Through-Hole (J-lead) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Technology | — | CMOS EPLD (erasable programmable logic device) |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| ライフサイクル状態 | — | Obsolete (legacy Altera Classic family) |