EP3SE260H780C2N vs EP3SE260H780C3N Vergleich
Detaillierter Direktvergleich von EP3SE260H780C2N von Intel und EP3SE260H780C3N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SE260H780C2N - Stratix III E FPGA 255K LE, 780-BGA | Intel
EP3SE260H780C2N ⚠ Letzte BestellmöglichkeitIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ AktivSpezifikationsvergleich
| Parameter | EP3SE260H780C2N | EP3SE260H780C3N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3.600,00 | $1.325,00 |
| Series | Stratix III E | Stratix® III E |
| Logic Elements | 255,000 | — |
| LABs / CLBs | 10,200 | — |
| Total RAM Bits | 16,672,768 | — |
| User I/O Count | 488 | — |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | — |
| Core Voltage | 0.9 V | — |
| Gehäuse | 780-BGA FCBGA | 780-BBGA, FCBGA (H780) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | Commercial (0C to +85C) | — |
| Speed Grade | C2 | — |
| MSL-Level | 3 (168 hours) | — |
| Reflow Peak Time Max | 40 s | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Package Code | BGA | — |
| Terminal Form | Ball | — |
| Number of Terminals | 780 | — |
| Process Node | 40 nm | — |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Betriebstemperatur | — | 0 °C to +85 °C (C grade, commercial) |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |